summaryrefslogtreecommitdiff
path: root/src/mainboard/intel
diff options
context:
space:
mode:
authorSubrata Banik <subrata.banik@intel.com>2021-09-29 15:33:55 +0530
committerSubrata Banik <subrata.banik@intel.com>2021-09-30 06:21:50 +0000
commitf72349d832180503304e68c1462f242699cb6c36 (patch)
tree4f2676ff62f4bbd9ed6c975d104800aa8de494b7 /src/mainboard/intel
parentdab80422571e03919a7c70592e053a08f9e89df1 (diff)
mb/intel/adlrvp: Update Rcomp target value for DDR4 RVP SKU
Update to recommended Rcomp drive strength value for DDR4 as per MRC team's input. Additionally, add space around the `targets` array. Change-Id: Ied63913db94b2e52ab394a66c70f7edfd507d99a Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/adlrvp/memory.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c
index 353cf4eff8..f93b361267 100644
--- a/src/mainboard/intel/adlrvp/memory.c
+++ b/src/mainboard/intel/adlrvp/memory.c
@@ -13,7 +13,7 @@ static const struct mb_cfg ddr4_mem_config = {
.resistor = 100,
/* Baseboard Rcomp target values */
- .targets = {40, 30, 33, 33, 30},
+ .targets = { 50, 20, 25, 25, 25 },
},
.ect = true, /* Early Command Training */
@@ -155,7 +155,7 @@ static const struct mb_cfg ddr5_mem_config = {
.resistor = 100,
/* Baseboard Rcomp target values */
- .targets = {50, 30, 30, 30, 27},
+ .targets = { 50, 30, 30, 30, 27 },
},
.ect = true, /* Early Command Training */