diff options
| author | Pratik Prajapati <pratikkumar.v.prajapati@intel.com> | 2015-08-13 15:21:37 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2015-08-19 14:04:19 +0000 |
| commit | f1acb9b69d9fca1b5396e76f5d19781dce46d01b (patch) | |
| tree | 536291e464b50970e8bc41d9d60837b61fbeed61 /src/mainboard/intel | |
| parent | 4938426783423889717e67f6be85e360a5f02d95 (diff) | |
Kunimitsu: Fix Wifi, kepler RP mapping and enable ClkReqSupport
(1) Wifi is connected on RP1 which is 1c.0 , so enabling
1c.0 and disabling 1d.0
(2) kepler is on RP5 which is 1c.4, so enabling it
(3) enabling ClkReqSupport for RP1 and RP5 so that L1 substates can
get enabled.
BRANCH=None
BUG=chrome-os-partner:43738
TEST=Built and boot for Kunimitsu. checked all PCIe powersaving
states (LTR, L1, L1S) are enabled
Original-Change-Id: I525661399d1a4d939b53d5ed5f7991598b84ddcd
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/293482
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Ib9a771a6ec137217668fb0385efc13b1824772b4
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: http://review.coreboot.org/11237
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/kunimitsu/devicetree.cb | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index e414928e02..09e41b97da 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -33,6 +33,8 @@ chip soc/intel/skylake register "PcieRpEnable[4]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkReqNumber[4]" = "2" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqSupport[4]" = "1" # GPE configuration register "gpe0_en_1" = "0x00000000" @@ -106,15 +108,15 @@ chip soc/intel/skylake device pci 19.0 on end # UART Controller #2 device pci 19.1 on end # I2C Controller #5 device pci 19.2 on end # I2C Controller #4 - device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.0 on end # PCI Express Port 1 device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.4 on end # PCI Express Port 5 device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 |