diff options
| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-02-24 13:33:45 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-03-13 00:46:55 +0100 |
| commit | e3fd63f264e1f6e2869cf5868e1810dff5641147 (patch) | |
| tree | 8c47722ba432db52850738723567547ad555b956 /src/mainboard/intel | |
| parent | 63db6142b6198fc3d6660e58228eeedd2eac59bd (diff) | |
northbridge/intel/i82810: Unify UDELAY selection
Instead of manually including udelay_io.c in each romstage,
select UDELAY_IO for all i810 boards in the chipset.
Change-Id: Ifda7dcfdf37b6affce838ee96ca6382b2d4be8c3
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13784
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/d810e2cb/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/d810e2cb/gpio.c | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/d810e2cb/romstage.c | 1 |
3 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/d810e2cb/Kconfig b/src/mainboard/intel/d810e2cb/Kconfig index 55a6bc6c2a..8695da962c 100644 --- a/src/mainboard/intel/d810e2cb/Kconfig +++ b/src/mainboard/intel/d810e2cb/Kconfig @@ -22,7 +22,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_SMSC_SMSCSUPERIO select HAVE_PIRQ_TABLE select USE_WATCHDOG_ON_BOOT - select UDELAY_TSC select BOARD_ROMSIZE_KB_512 config MAINBOARD_DIR diff --git a/src/mainboard/intel/d810e2cb/gpio.c b/src/mainboard/intel/d810e2cb/gpio.c index 6241435890..84e49d69a6 100644 --- a/src/mainboard/intel/d810e2cb/gpio.c +++ b/src/mainboard/intel/d810e2cb/gpio.c @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include <delay.h> + #define PME_DEV PNP_DEV(0x4e, 0x0a) #define PME_IO_BASE_ADDR 0x800 /* Runtime register base address */ diff --git a/src/mainboard/intel/d810e2cb/romstage.c b/src/mainboard/intel/d810e2cb/romstage.c index 2f31a0d521..934cb173a1 100644 --- a/src/mainboard/intel/d810e2cb/romstage.c +++ b/src/mainboard/intel/d810e2cb/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <southbridge/intel/i82801bx/i82801bx.h> #include <northbridge/intel/i82810/raminit.h> -#include "drivers/pc80/udelay_io.c" #include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include "gpio.c" |