diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2021-10-15 13:37:47 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-11-17 00:35:59 +0000 |
| commit | db85b096d454576e2d75ea5976b86c4460517d0e (patch) | |
| tree | 05b0e78621d600eec6e9a3831ef4bfc578c703f1 /src/mainboard/intel | |
| parent | 86a9cdd589c71458629797e2cfc86ce1d4e82235 (diff) | |
mb/intel/adlrvp: Fix sagv point3 clipping to 4800Mhz
Update board type to 4 as per MRC team's input. This
fixes LP5 sagv point 3 being clipped from the expected
5200Mhz to 4800Mhz.
TEST=Boot to OS, verify frequency locked.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I9472aec41537425c1ed648b949f484939ee9ff99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/adlrvp/memory.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index 93f1aa3a25..f4ae5416d5 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -227,7 +227,7 @@ static const struct mb_cfg adlm_lp4_mem_config = { .LpDdrDqDqsReTraining = 1, - .UserBd = BOARD_TYPE_ULT_ULX, + .UserBd = BOARD_TYPE_ULT_ULX_T4, }; static const struct mb_cfg adlm_lp5_mem_config = { @@ -283,7 +283,7 @@ static const struct mb_cfg adlm_lp5_mem_config = { .ect = false, /* Early Command Training */ - .UserBd = BOARD_TYPE_ULT_ULX, + .UserBd = BOARD_TYPE_ULT_ULX_T4, .lp5x_config = { .ccc_config = 0xff, |