diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2019-01-28 12:11:06 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2019-01-29 04:30:16 +0000 |
| commit | c1bf8ccdbc2aa2d50d52b049aa5875ff7064c5fd (patch) | |
| tree | 43f16a244a64701750a8fab4a7a41158fe421bdd /src/mainboard/intel | |
| parent | e990577d05718ed789e0e60e6e7e67f260ef1bf5 (diff) | |
mb/intel/icelake_rvp/../icl_y: Enable SaGv
This patch enables SaGv on Intel ICL-Y RVP board.
TEST=Able to build and boot to Chrome OS.
Change-Id: Ic3ed94d47ddc7fd70bf3de1db15fe574029df856
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb index 0972c29e12..4f4130853e 100644 --- a/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb +++ b/src/mainboard/intel/icelake_rvp/variants/icl_y/devicetree.cb @@ -13,7 +13,7 @@ chip soc/intel/icelake register "gpe0_dw2" = "GPP_E" # FSP configuration - register "SaGv" = "SaGv_Disabled" + register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" register "ScsEmmcHs400Enabled" = "1" register "SdCardPowerEnableActiveHigh" = "1" |