chromeos mainboards: remove chromeos.asl

Use the ACPI generator for creating the Chrome OS gpio
package. Each mainboard has its own list of Chrome OS
gpios that are fed into a helper to generate the ACPI
external OIPG package.  Additionally, the common
chromeos.asl is now conditionally included based on
CONFIG_CHROMEOS.

Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

23 files changed, 77 insertions, 151 deletions

diff --git a/src/mainboard/intel/amenia/acpi/chromeos.asl b/src/mainboard/intel/amenia/acpi/chromeos.asl
deleted file mode 100644
index 31d0afc8c3..0000000000
--- a/src/mainboard/intel/amenia/acpi/chromeos.asl
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2016 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/gpio_defs.h>
-
-Name (OIPG, Package () {
-	/* No physical recovery GPIO. */
-	Package () { 0x0001, 0, 0xFFFFFFFF, "INT3452:01" },
-	/* Firmware write protect GPIO. */
-	Package () { 0x0003, 1, PAD_NW(GPIO_75), "INT3452:01" },
-})
diff --git a/src/mainboard/intel/amenia/chromeos.c b/src/mainboard/intel/amenia/chromeos.c
index b6669bf0e0..4cfc2a62a9 100644
--- a/src/mainboard/intel/amenia/chromeos.c
+++ b/src/mainboard/intel/amenia/chromeos.c
@@ -18,6 +18,7 @@
 #include "ec.h"
 
 #include <ec/google/chromeec/ec.h>
+#include <soc/gpio_defs.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 int get_lid_switch(void)
@@ -48,3 +49,13 @@ int get_write_protect_state(void)
 {
 	return 0;
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME),
+	CROS_GPIO_WP_AH(PAD_NW(GPIO_75), GPIO_COMM_NW_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl
index 7602b1e80d..9314469d88 100644
--- a/src/mainboard/intel/amenia/dsdt.asl
+++ b/src/mainboard/intel/amenia/dsdt.asl
@@ -39,10 +39,7 @@ DefinitionBlock(
 		}
 	}
 
-	#if IS_ENABLED(CONFIG_CHROMEOS)
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
-	#endif
 
 	/* Mainboard Specific devices */
 	#include "acpi/mainboard.asl"
diff --git a/src/mainboard/intel/baskingridge/acpi/chromeos.asl b/src/mainboard/intel/baskingridge/acpi/chromeos.asl
deleted file mode 100644
index 9c49265331..0000000000
--- a/src/mainboard/intel/baskingridge/acpi/chromeos.asl
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
-	Package () { 0x0001, 1, 69, "LynxPoint" }, // recovery
-	Package () { 0x0002, 0, 48, "LynxPoint" }, // developer
-	Package () { 0x0003, 0, 22, "LynxPoint" }, // firmware write protect
-})
diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c
index 94e8d89a06..1666fc5528 100644
--- a/src/mainboard/intel/baskingridge/chromeos.c
+++ b/src/mainboard/intel/baskingridge/chromeos.c
@@ -20,6 +20,7 @@
 #include <device/pci.h>
 #include <southbridge/intel/lynxpoint/pch.h>
 #include <southbridge/intel/common/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #ifndef __PRE_RAM__
 #include <boot/coreboot_tables.h>
@@ -102,3 +103,14 @@ int get_write_protect_state(void)
 {
 	return 0;
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AH(69, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_DEV_AL(48, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AL(22, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/intel/baskingridge/dsdt.asl b/src/mainboard/intel/baskingridge/dsdt.asl
index 5cd0ffb91b..e4b489cda5 100644
--- a/src/mainboard/intel/baskingridge/dsdt.asl
+++ b/src/mainboard/intel/baskingridge/dsdt.asl
@@ -48,7 +48,6 @@ DefinitionBlock(
 		}
 	}
 
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	/* Chipset specific sleep states */
diff --git a/src/mainboard/intel/baskingridge/mainboard.c b/src/mainboard/intel/baskingridge/mainboard.c
index 4c7baca5eb..dbf3574e34 100644
--- a/src/mainboard/intel/baskingridge/mainboard.c
+++ b/src/mainboard/intel/baskingridge/mainboard.c
@@ -28,6 +28,7 @@
 #include <arch/interrupt.h>
 #include <boot/coreboot_tables.h>
 #include <southbridge/intel/lynxpoint/pch.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 void mainboard_suspend_resume(void)
 {
@@ -35,13 +36,12 @@ void mainboard_suspend_resume(void)
 	outb(0xcb, 0xb2);
 }
 
-
-
 // mainboard_enable is executed as first thing after
 // enumerate_buses().
 
 static void mainboard_enable(device_t dev)
 {
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 }
 
diff --git a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl b/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl
deleted file mode 100644
index 9f2e54a9d0..0000000000
--- a/src/mainboard/intel/emeraldlake2/acpi/chromeos.asl
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
-	Package() { 0x001, 0, 22, "CougarPoint" }, // recovery button
-	Package() { 0x002, 1, 57, "CougarPoint" }, // developer switch
-	Package() { 0x003, 0, 48, "CougarPoint" }, // firmware write protect
-})
diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c
index bb4ebe9f54..896f8767f8 100644
--- a/src/mainboard/intel/emeraldlake2/chromeos.c
+++ b/src/mainboard/intel/emeraldlake2/chromeos.c
@@ -20,6 +20,7 @@
 #include <device/pci.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #ifndef __PRE_RAM__
 #include <boot/coreboot_tables.h>
@@ -91,3 +92,14 @@ int get_recovery_mode_switch(void)
 	/* Recovery: GPIO22, active low */
 	return !get_gpio(22);
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(22, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_DEV_AH(57, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AL(48, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/intel/emeraldlake2/dsdt.asl b/src/mainboard/intel/emeraldlake2/dsdt.asl
index 8d9e281def..a31c415000 100644
--- a/src/mainboard/intel/emeraldlake2/dsdt.asl
+++ b/src/mainboard/intel/emeraldlake2/dsdt.asl
@@ -49,7 +49,6 @@ DefinitionBlock(
 		}
 	}
 
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	/* Chipset specific sleep states */
diff --git a/src/mainboard/intel/emeraldlake2/mainboard.c b/src/mainboard/intel/emeraldlake2/mainboard.c
index a0fd9e831f..654b1de476 100644
--- a/src/mainboard/intel/emeraldlake2/mainboard.c
+++ b/src/mainboard/intel/emeraldlake2/mainboard.c
@@ -28,12 +28,14 @@
 #include <arch/interrupt.h>
 #include <boot/coreboot_tables.h>
 #include <southbridge/intel/bd82x6x/pch.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 // mainboard_enable is executed as first thing after
 // enumerate_buses().
 
 static void mainboard_enable(device_t dev)
 {
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 }
 
diff --git a/src/mainboard/intel/kunimitsu/acpi/chromeos.asl b/src/mainboard/intel/kunimitsu/acpi/chromeos.asl
deleted file mode 100644
index 4fc5f22984..0000000000
--- a/src/mainboard/intel/kunimitsu/acpi/chromeos.asl
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "../gpio.h"
-
-Name (OIPG, Package () {
-	/* No physical recovery GPIO. */
-	Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" },
-	/* Firmware write protect GPIO. */
-	Package () { 0x0003, 1, GPIO_PCH_WP, "INT344B:00" },
-})
diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c
index 1e0bd3c093..daa85c69e0 100644
--- a/src/mainboard/intel/kunimitsu/chromeos.c
+++ b/src/mainboard/intel/kunimitsu/chromeos.c
@@ -82,3 +82,13 @@ int get_write_protect_state(void)
 	/* Read PCH_WP GPIO. */
 	return gpio_get(GPIO_PCH_WP);
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/intel/kunimitsu/dsdt.asl b/src/mainboard/intel/kunimitsu/dsdt.asl
index c9e13e7e45..b5a37c68cc 100644
--- a/src/mainboard/intel/kunimitsu/dsdt.asl
+++ b/src/mainboard/intel/kunimitsu/dsdt.asl
@@ -45,7 +45,6 @@ DefinitionBlock(
 	}
 
 	// Chrome OS specific
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	// Chipset specific sleep states
diff --git a/src/mainboard/intel/kunimitsu/mainboard.c b/src/mainboard/intel/kunimitsu/mainboard.c
index d634fac147..9f79db6ebc 100644
--- a/src/mainboard/intel/kunimitsu/mainboard.c
+++ b/src/mainboard/intel/kunimitsu/mainboard.c
@@ -22,6 +22,7 @@
 #include <stdlib.h>
 #include <string.h>
 #include <soc/nhlt.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "ec.h"
 #include "gpio.h"
 
@@ -99,6 +100,7 @@ static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/intel/strago/acpi/chromeos.asl b/src/mainboard/intel/strago/acpi/chromeos.asl
deleted file mode 100644
index c470ca3e9d..0000000000
--- a/src/mainboard/intel/strago/acpi/chromeos.asl
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
- * Fields are in the following order.
- * - Type: recovery = 1 developer mode = 2 write protect = 3
- * - Active Level - if -1 not a valid gpio
- * - GPIO number encoding - if -1 not a valid gpio
- * - Chipset Name
- *
- * Note: We need to encode gpios within the 4 separate banks
- * with the MMIO offset of each banks space. e.g. MF_ISH_GPIO_4 would be encoded
- * as 0x10013 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000.
- */
-
-Name(OIPG, Package() {
-	/* No physical recovery button */
-	Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" },
-	Package () { 0x0003, 1, 0x10013, "Braswell" },
-})
diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c
index 0e072f0dc0..0fb98111a8 100644
--- a/src/mainboard/intel/strago/chromeos.c
+++ b/src/mainboard/intel/strago/chromeos.c
@@ -118,3 +118,13 @@ int get_write_protect_state(void)
 	/* WP is enabled when the pin is reading high. */
 	return !!gpio_get(WP_GPIO);
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(0x10013, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/intel/strago/dsdt.asl b/src/mainboard/intel/strago/dsdt.asl
index f1248d8d7c..59af6ddb95 100644
--- a/src/mainboard/intel/strago/dsdt.asl
+++ b/src/mainboard/intel/strago/dsdt.asl
@@ -54,7 +54,6 @@ DefinitionBlock(
 			#include <soc/intel/common/acpi/wifi.asl>
 		}
 	}
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	/* Chipset specific sleep states */
diff --git a/src/mainboard/intel/strago/mainboard.c b/src/mainboard/intel/strago/mainboard.c
index 0566c8e2f6..71ba62b13e 100644
--- a/src/mainboard/intel/strago/mainboard.c
+++ b/src/mainboard/intel/strago/mainboard.c
@@ -18,6 +18,7 @@
 #include <bootstate.h>
 #include <device/device.h>
 #include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "ec.h"
 
 static void mainboard_init(device_t dev)
@@ -32,6 +33,7 @@ static void mainboard_init(device_t dev)
 static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 }
 
 
diff --git a/src/mainboard/intel/wtm2/acpi/chromeos.asl b/src/mainboard/intel/wtm2/acpi/chromeos.asl
deleted file mode 100644
index 4257e7ddfe..0000000000
--- a/src/mainboard/intel/wtm2/acpi/chromeos.asl
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
-	Package () { 0x0001, 0, 0xFFFFFFFF, "PCH-LP" }, // recovery
-	Package () { 0x0002, 0, 0xFFFFFFFF, "PCH-LP" }, // developer
-	Package () { 0x0003, 0, 0xFFFFFFFF, "PCH-LP" }, // firmware write protect
-})
diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c
index feee0cbc32..862f4a411c 100644
--- a/src/mainboard/intel/wtm2/chromeos.c
+++ b/src/mainboard/intel/wtm2/chromeos.c
@@ -19,6 +19,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /* Compile-time settings for developer and recovery mode. */
 #define DEV_MODE_SETTING 1
@@ -55,3 +56,14 @@ int get_write_protect_state(void)
 {
 	return 0;
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_DEV_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl
index 1601483921..410f6d20aa 100644
--- a/src/mainboard/intel/wtm2/dsdt.asl
+++ b/src/mainboard/intel/wtm2/dsdt.asl
@@ -49,7 +49,6 @@ DefinitionBlock(
 	#include "acpi/thermal.asl"
 
 	// Chrome OS specific
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	// Chipset specific sleep states
diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c
index 253e8ff03c..ffb5b86a18 100644
--- a/src/mainboard/intel/wtm2/mainboard.c
+++ b/src/mainboard/intel/wtm2/mainboard.c
@@ -27,6 +27,7 @@
 #include <arch/io.h>
 #include <arch/interrupt.h>
 #include <boot/coreboot_tables.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 void mainboard_suspend_resume(void)
 {
@@ -39,6 +40,7 @@ void mainboard_suspend_resume(void)
 
 static void mainboard_enable(device_t dev)
 {
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 }