mb/intel/shadowmountain: Add the ramstage code

This patch includes the ramstage changes for the
shadowmountain board.

BUG=b:175808146
TEST= Build and boot shadowmountain board.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I419eecefddf9ee6e4249ada041ebeb1b78e85eb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49732
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

11 files changed, 726 insertions, 9 deletions

diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig
index 9273a11db5..6a5abc160d 100644
--- a/src/mainboard/intel/shadowmountain/Kconfig
+++ b/src/mainboard/intel/shadowmountain/Kconfig
@@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS
 	select BOARD_ROMSIZE_KB_32768
 	select DRIVERS_I2C_GENERIC
 	select DRIVERS_I2C_HID
+	select DRIVERS_I2C_MAX98373
 	select DRIVERS_INTEL_DPTF
 	select DRIVERS_INTEL_PMC
 	select DRIVERS_SPI_ACPI
diff --git a/src/mainboard/intel/shadowmountain/Makefile.inc b/src/mainboard/intel/shadowmountain/Makefile.inc
index a4172c7134..54065475cc 100644
--- a/src/mainboard/intel/shadowmountain/Makefile.inc
+++ b/src/mainboard/intel/shadowmountain/Makefile.inc
@@ -9,6 +9,10 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c
 romstage-y += romstage.c
 
 ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += ec.c
+ramstage-y += mainboard.c
+
+smm-y += smihandler.c
 
 subdirs-y += spd
 
diff --git a/src/mainboard/intel/shadowmountain/ec.c b/src/mainboard/intel/shadowmountain/ec.c
new file mode 100644
index 0000000000..e9dc63b527
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/ec.c
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec.h>
+#include <baseboard/ec.h>
+
+void mainboard_ec_init(void)
+{
+	static const struct google_chromeec_event_info info = {
+		.log_events = MAINBOARD_EC_LOG_EVENTS,
+		.sci_events = MAINBOARD_EC_SCI_EVENTS,
+		.s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
+		.s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
+		.s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
+	};
+
+	google_chromeec_events_init(&info, acpi_is_wakeup_s3());
+}
diff --git a/src/mainboard/intel/shadowmountain/mainboard.c b/src/mainboard/intel/shadowmountain/mainboard.c
new file mode 100644
index 0000000000..2783b4d2ce
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/mainboard.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <device/device.h>
+#include <ec/ec.h>
+#include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+static void mainboard_init(void *chip_info)
+{
+	const struct pad_config *base_pads;
+	const struct pad_config *override_pads;
+	size_t base_num, override_num;
+
+	base_pads = variant_base_gpio_table(&base_num);
+	override_pads = variant_override_gpio_table(&override_num);
+
+	gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num);
+
+	mainboard_ec_init();
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/intel/shadowmountain/smihandler.c b/src/mainboard/intel/shadowmountain/smihandler.c
new file mode 100644
index 0000000000..e20135b081
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/smihandler.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <cpu/x86/smm.h>
+#include <ec/google/chromeec/smm.h>
+#include <intelblocks/smihandler.h>
+#include <baseboard/ec.h>
+
+void mainboard_smi_espi_handler(void)
+{
+	chromeec_smi_process_events();
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+	if (!CONFIG(EC_GOOGLE_CHROMEEC))
+		return;
+
+	chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+	if (CONFIG(EC_GOOGLE_CHROMEEC))
+		chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);
+
+	return 0;
+}
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc b/src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc
index 304ce1110d..0fe30e81bc 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc
@@ -3,3 +3,5 @@
 bootblock-y += early_gpio.c
 
 romstage-y += memory.c
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
index 088b595e93..c0d7864f28 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -12,6 +12,27 @@ chip soc/intel/alderlake
 	register "pmc_gpe0_dw1" = "GPP_D"
 	register "pmc_gpe0_dw2" = "GPP_E"
 
+	# Enable heci communication
+	register "HeciEnabled" = "1"
+
+	# FSP configuration
+	register "SaGv" = "SaGv_Disabled"
+
+	# S0ix enable
+	register "s0ix_enable" = "1"
+
+	register "usb2_ports[0]" = "USB2_PORT_MID(OC1)"		# Type-A Port A0
+	register "usb2_ports[1]" = "USB2_PORT_MID(OC2)"		# Type-A Port A1
+	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 WWAN
+	register "usb2_ports[3]" = "USB2_PORT_MID(OC0)"		# Type-A / Type-C Cl
+	register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Camera
+	register "usb2_ports[5]" = "USB2_PORT_MID(OC3)"		# Type-A / Type-C Co
+	register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)"	# M.2 Bluetooth
+
+	register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)"	# USB3/2 Type A port A0
+	register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)"	# USB3/2 Type A port A1
+	register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)"	# M.2 WWAN
+
 	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
 	register "gen1_dec" = "0x00fc0801"
 	register "gen2_dec" = "0x000c0201"
@@ -40,6 +61,123 @@ chip soc/intel/alderlake
 		.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR,
 	}"
 
+	# Enable SATA
+	register "SataEnable" = "1"
+	register "SataMode" = "0"
+	register "SataSalpSupport" = "1"
+	register "SataPortsEnable[0]" = "0"
+	register "SataPortsEnable[1]" = "1"
+	register "SataPortsDevSlp[0]" = "0"
+	register "SataPortsDevSlp[1]" = "1"
+	register "SataPortsEnableDitoConfig[1]" = "1"
+
+	register "SerialIoI2cMode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C2]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C3]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C4]  = PchSerialIoDisabled,
+		[PchSerialIoIndexI2C5]  = PchSerialIoPci,
+	}"
+
+	register "SerialIoGSpiMode" = "{
+		[PchSerialIoIndexGSPI0] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI1] = PchSerialIoPci,
+		[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
+		[PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
+	}"
+
+	register "SerialIoGSpiCsMode" = "{
+		[PchSerialIoIndexGSPI0] = 1,
+		[PchSerialIoIndexGSPI1] = 1,
+	}"
+
+	register "SerialIoGSpiCsState" = "{
+		[PchSerialIoIndexGSPI0] = 1,
+		[PchSerialIoIndexGSPI1] = 1,
+	}"
+
+	register "SerialIoUartMode" = "{
+		[PchSerialIoIndexUART0] = PchSerialIoPci,
+		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
+		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
+	}"
+
+	# HD Audio
+	register "PchHdaDspEnable" = "1"
+	register "PchHdaAudioLinkHdaEnable" = "0"
+	register "PchHdaAudioLinkDmicEnable[0]" = "0"
+	register "PchHdaAudioLinkDmicEnable[1]" = "0"
+	register "PchHdaAudioLinkSspEnable[0]" = "0"
+	register "PchHdaAudioLinkSspEnable[1]" = "0"
+	register "PchHdaAudioLinkSndwEnable[0]" = "0"
+	register "PchHdaAudioLinkSndwEnable[1]" = "0"
+	# iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T
+	register "PchHdaIDispLinkTmode" = "2"
+	# iDisp-Link Freq 4: 96MHz, 3: 48MHz.
+	register "PchHdaIDispLinkFrequency" = "4"
+	# Not disconnected/enumerable
+	register "PchHdaIDispCodecDisconnect" = "0"
+
+	# DP port
+	register "DdiPortAConfig" = "1"	# eDP
+	register "DdiPortBConfig" = "0"
+
+	register "DdiPortAHpd" = "1"
+	register "DdiPortBHpd" = "1"
+	register "DdiPortCHpd" = "0"
+	register "DdiPort1Hpd" = "1"
+	register "DdiPort2Hpd" = "1"
+	register "DdiPort3Hpd" = "0"
+	register "DdiPort4Hpd" = "0"
+
+	register "DdiPortADdc" = "0"
+	register "DdiPortBDdc" = "1"
+	register "DdiPortCDdc" = "0"
+	register "DdiPort1Ddc" = "0"
+	register "DdiPort2Ddc" = "0"
+	register "DdiPort3Ddc" = "0"
+	register "DdiPort4Ddc" = "0"
+
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| chipset_lockdown  | CHIPSET_LOCKDOWN_COREBOOT |
+	#| GSPI0             | cr50 TPM. Early init is   |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#|                   | before memory is up       |
+	#| GSPI1             | Fingerprint MCU           |
+	#| I2C0              | SAR0, WWAN, HDMI          |
+	#| I2C1              | Camera                    |
+	#| I2C2              | Audio                     |
+	#| I2C3              | Touchscreen, USI          |
+	#| I2C5              | Trackpad                  |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+		.gspi[0] = {
+			.speed_mhz = 1,
+			.early_init = 1,
+		},
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[1] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[2] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[3] = {
+			.speed = I2C_SPEED_FAST,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+		},
+	}"
+
 	device domain 0 on
 		device pci 00.0 on  end # Host Bridge
 		device pci 02.0 on  end # Graphics
@@ -74,13 +212,59 @@ chip soc/intel/alderlake
 		device pci 12.6 off end # GSPI2
 		device pci 13.0 off end # GSPI3
 		device pci 13.1 off end
-		device pci 14.0 on  end # USB3.1 xHCI
+		device pci 14.0 on
+			chip drivers/usb/acpi
+				register "desc" = ""Root Hub""
+				register "type" = "UPC_TYPE_HUB"
+				device usb 0.0 on
+					chip drivers/usb/acpi
+						register "desc" = ""Bluetooth""
+						register "type" = "UPC_TYPE_INTERNAL"
+						device usb 2.9 on end
+					end
+				end
+			end
+		end # USB3.1 xHCI
 		device pci 14.1 off end # USB3.1 xDCI
 		device pci 14.2 off end # Shared RAM
-		device pci 14.3 on  end # CNVi: WiFi
+		device pci 14.3 on
+			chip drivers/wifi/generic
+				register "wake" = "GPE0_PME_B0"
+				device generic 0 on end
+			end
+		end # CNVi: WiFi
 		device pci 15.0 on  end # I2C0
 		device pci 15.1 on  end # I2C1
-		device pci 15.2 on  end # I2C2
+		device pci 15.2 on
+			chip drivers/i2c/generic
+				register "hid" = ""10EC5682""
+				register "name" = ""RT58""
+				register "desc" = ""Headset Codec""
+				register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_F9)"
+				# Set the jd_src to RT5668_JD1 for jack detection
+				register "property_count" = "1"
+				register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
+				register "property_list[0].name" = ""realtek,jd-src""
+				register "property_list[0].integer" = "1"
+				device i2c 1a on end
+			end
+			chip drivers/i2c/max98373
+				register "vmon_slot_no" = "0"
+				register "imon_slot_no" = "1"
+				register "uid" = "0"
+				register "desc" = ""Right Speaker Amp""
+				register "name" = ""MAXR""
+				device i2c 31 on end
+			end
+			chip drivers/i2c/max98373
+				register "vmon_slot_no" = "2"
+				register "imon_slot_no" = "3"
+				register "uid" = "1"
+				register "desc" = ""Left Speaker Amp""
+				register "name" = ""MAXL""
+				device i2c 32 on end
+			end
+		end # I2C2
 		device pci 15.3 on  end # I2C3
 		device pci 16.0 off end # HECI1
 		device pci 16.1 off end # HECI2
@@ -90,7 +274,16 @@ chip soc/intel/alderlake
 		device pci 16.5 off end # HECI4
 		device pci 17.0 on  end # SATA
 		device pci 19.0 off end # I2C4
-		device pci 19.1 on  end # I2C5
+		device pci 19.1 on
+			chip drivers/i2c/generic
+				register "hid" = ""ELAN0000""
+				register "desc" = ""ELAN Touchpad""
+				register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)"
+				register "wake" = "GPE0_DW2_15"
+				register "probed" = "1"
+				device i2c 15 on end
+			end
+		end # I2C5
 		device pci 19.2 off end # UART2
 		device pci 1c.0 off end # RP1
 		device pci 1c.1 off end # RP2
@@ -114,7 +307,7 @@ chip soc/intel/alderlake
 			end
 		end # eSPI
 		device pci 1f.1 on  end # P2SB
-		device pci 1f.2 hidden  end # PMC
+		device pci 1f.2 hidden end # PMC
 		device pci 1f.3 on  end # Intel Audio SNDW
 		device pci 1f.4 on  end # SMBus
 		device pci 1f.5 on  end # SPI
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c b/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c
index 29e6184447..80a42646fc 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/early_gpio.c
@@ -21,15 +21,16 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_GPI(GPP_A20, NONE, DEEP),
 	/* B11 : PCH_WP_OD */
 	PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
-
 	/* C0 : EN_PP3300_WLAN */
 	PAD_CFG_GPO(GPP_C0, 1, DEEP),
 	/* C3 : H1_PCH_INT_ODL */
 	PAD_CFG_GPI_APIC(GPP_C3, NONE, PLTRST, LEVEL, INVERT),
-
 	/* D10 : EN_PP3300_WWAN */
 	PAD_CFG_GPO(GPP_D10, 1, DEEP),
-
+	/* D15 : MEM_STRAP_3 */
+	PAD_NC(GPP_D15, NONE),
+	/* D16 : EN_PP3300_SD */
+	PAD_NC(GPP_D16, UP_20K),
 	/* E10 : PCH_GSPI0_H1_TPM_CS_L */
 	PAD_CFG_NF(GPP_E10, NONE, DEEP, NF7),
 	/* E11 : PCH_GSPI0_H1_TPM_CLK */
@@ -38,7 +39,6 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_E12, NONE, DEEP, NF7),
 	/* E13 : PCH_GSPI0_H1_TPM_MOSI_STRAP */
 	PAD_CFG_NF(GPP_E13, NONE, DEEP, NF7),
-
 	/* F14 : WLAN_PERST_L */
 	PAD_CFG_GPO(GPP_F14, 1, DEEP),
 	/* F20 : WWAN_RST_ODL
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c b/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c
new file mode 100644
index 0000000000..090715e25c
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c
@@ -0,0 +1,361 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+/* Leave eSPI pins untouched from default settings */
+static const struct pad_config gpio_table[] = {
+	/* A0 thru A4 and A9/10 come configured out of reset, do not touch */
+	/* A0  : ESPI_IO0 ==> ESPI_IO_0 */
+	/* A1  : ESPI_IO1 ==> ESPI_IO_1 */
+	/* A2  : ESPI_IO2 ==> ESPI_IO_2 */
+	/* A3  : ESPI_IO3 ==> ESPI_IO_3 */
+	/* A4  : ESPI_CS# ==> ESPI_CS_L */
+	/* A9  : ESPI_CLK ==> ESPI_CLK */
+	/* A10  : ESPI_RESET ==> ESPI_RESET */
+	/* A5 : USB_C0_AUXP_DC */
+	PAD_CFG_GPO(GPP_A5, 1, DEEP),
+	/* A6 : USB_C0_AUXN_DC */
+	PAD_CFG_GPO(GPP_A6, 1, DEEP),
+	/* A8 : EC_IN_RW_OD */
+	PAD_CFG_GPI(GPP_A8, NONE, DEEP),
+	/* A11 : SSD_PERST_L */
+	PAD_CFG_GPO(GPP_A11, 1, DEEP),
+	/* A12 : M2_SSD_PEDET */
+	PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+	/* A13 : BT_DISABLE_L */
+	PAD_CFG_GPO(GPP_A13, 1, DEEP),
+	/* A14 : USB_OC1# ==> USB_A0_OC_ODL */
+	PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+	/* A15 : USB_OC2# ==> USB_A1_OC_ODL */
+	PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+	/* A16 : USB_C0_OC_ODL */
+	PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+	/* A17 : DDSP_HPDC ==> MEM_CH_SEL */
+	PAD_CFG_GPI(GPP_A17, NONE, DEEP),
+	/* A18 : HDMI_HPD */
+	PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+	/* A21 : EN_FP_PWR */
+	PAD_CFG_GPO(GPP_A21, 1, DEEP),
+	/* A22 : EN_HDMI_PWR */
+	PAD_CFG_GPO(GPP_A22, 1, DEEP),
+	/* A23 : EN_SPKR_PA */
+	PAD_CFG_GPO(GPP_A23, 1, DEEP),
+
+	/* B0  : CORE_VID0 */
+	PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+	/* B1  : CORE_VID1 */
+	PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+	/* B2  : VRALERT# ==> VRALERT_L */
+	PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
+	/* B3 : PEN_DET_ODL */
+	PAD_CFG_GPI(GPP_B3, NONE, DEEP),
+	/* B4 : WiFi_DISABLE_L */
+	PAD_CFG_GPO(GPP_B4, 1, DEEP),
+	/* B5 : ISH_I2C0_CVF_SDA */
+	PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
+	/* B6 : ISH_I2C0_CVF_SCL */
+	PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
+	/* B7 : ISH_I2C0_SENSOR_SDA */
+	PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
+	/* B8 : ISH_I2C0_SENSOR_SCL */
+	PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+	/* B11 : PMCALERT# ==> PCH_WP_OD */
+	PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
+	/* B12 : SLP_S0# ==> SLP_S0_L */
+	PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+	/* B13 : PLTRST# ==> PLT_RST_L */
+	PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+	/* B14 : SPKR ==> GPP_B14_STRAP */
+	PAD_NC(GPP_B14, NONE),
+	/* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
+	PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+	/* B15 : FPMCU_INT_L */
+	PAD_CFG_GPI_INT(GPP_B15, NONE, PLTRST, LEVEL),
+	/* B16 : PCH_I2C5_TRACKPAD_SDA */
+	PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
+	/* B17 : PCH_I2C5_TRACKPAD_SCL */
+	PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2),
+	/* B18 : EN_PP5000_TRACKPAD */
+	PAD_CFG_GPO(GPP_B18, 1, DEEP),
+	/* B23 : SML1ALERT# ==> GPP_B23_STRAP # */
+	PAD_NC(GPP_B23, NONE),
+
+	/* C0 : EN_PP3300_WLAN */
+	PAD_CFG_GPO(GPP_C0, 1, DEEP),
+	/* C1 : USI_RST_L */
+	PAD_CFG_GPO(GPP_C1, 0, DEEP),
+	/* C2  : SMBALERT# ==> GPP_C2_STRAP */
+	PAD_NC(GPP_C2, NONE),
+	/* C3 : H1_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_C3, NONE, PLTRST, LEVEL, INVERT),
+	/* C4 : EN_PP5000_PEN */
+	PAD_CFG_GPO(GPP_C4, 1, DEEP),
+	/* C5  : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */
+	PAD_NC(GPP_C5, NONE),
+	/* C6  : SML1CLK ==> EC_PCH_INT_ODL */
+	PAD_CFG_GPI_APIC(GPP_C6, NONE, PLTRST, LEVEL, INVERT),
+	/* C7 : FPMCU_RST_ODL */
+	PAD_CFG_GPO(GPP_C7, 1, DEEP),
+
+	/* D0 : SSD_RTD3_EN */
+	PAD_CFG_GPO(GPP_D0, 1, DEEP),
+	/* D1 : ISH_ACCEL_INT_L */
+	PAD_NC(GPP_D1, NONE),
+	/* D2 : ISH_LID_OPEN */
+	PAD_NC(GPP_D2, NONE),
+	/* D3 : ISH_ALS_RGB_INT_L */
+	PAD_NC(GPP_D3, NONE),
+	/* D4 : FCAM_RST_L */
+	PAD_CFG_GPO(GPP_D4, 0, PLTRST),
+	/* D5  : SRCCLKREQ0$ ==> SSD_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+	/* D6 : WLAN_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+	/* D7  : SRCCLKREQ2# ==> NC */
+	PAD_NC(GPP_D7, NONE),
+	/* D8 : SD_CLKREQ_ODL */
+	PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+	/* D9 : SD_PE_WAKE_ODL */
+	PAD_CFG_GPI(GPP_D9, NONE, DEEP),
+	/* D10 : EN_PP3300_WWAN */
+	PAD_CFG_GPO(GPP_D10, 1, DEEP),
+	/* D11 : PEN_ALERT_ODL */
+	PAD_CFG_GPI(GPP_D11, NONE, DEEP),
+	/* D12 : PCH_FPMCU_BOOT0 */
+	PAD_CFG_GPO(GPP_D12, 0, DEEP),
+	/* D13 : UART_ISH_RX_DEBUG_TX */
+	PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+	/* D14 : UART_ISH_TX_DEBUG_RX */
+	PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
+	/* D15 : ISH_UART0_RTS# ==> MEM_STRAP_3 */
+	PAD_NC(GPP_D15, NONE),
+	/* D16 : EN_PP3300_SD */
+	PAD_CFG_GPO(GPP_D16, 1, DEEP),
+	/* D17 : EN_FCAM_PWR */
+	PAD_CFG_GPO(GPP_D17, 0, DEEP),
+	/* D18 : FCAM_SNRPWR_EN */
+	PAD_CFG_GPO(GPP_D18, 0, DEEP),
+	/* D19 : I2S_MCLK1 ==> I2S_MCLK1 */
+	PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+
+	/* E0  : SATAXPCIE0 ==> USB_A1_RT_RST_ODL */
+	PAD_CFG_GPO(GPP_E0, 1, DEEP),
+	/* E1 : PEN_DET_ODL */
+	PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE),
+	/* E2 : WLAN_PCIE_WAKE_ODL */
+	PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+	/* E3 : USI_REPORT_EN */
+	PAD_CFG_GPO(GPP_E3, 0, DEEP),
+	/* E4  : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */
+	PAD_NC(GPP_E4, NONE),
+	/* E5  : SATA_DEVSLP1 ==> M2_SSD_DEVSLP_OD */
+	PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
+	/* E6  : THC0_SPI1_RST# ==> GPPE6_STRAP */
+	PAD_NC(GPP_E6, NONE),
+	/* E7 : USI_INT */
+	PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE),
+	/* E8 : SLP_S0IX */
+	PAD_CFG_GPO(GPP_E8, 0, DEEP),
+	/* E9  : USB2_OC0# ==> USB_C1_OC_ODL */
+	PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+	/* E14 : DDPC_HPDA ==> SOC_EDP_HPD */
+	PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+	/* E15 : TRACKPAD_INT_ODL */
+	PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT),
+	/* E16 : WWAN_SIM1_DET_OD */
+	PAD_CFG_GPI(GPP_E16, NONE, DEEP),
+	/* E17 : WWAN_PERST_L */
+	PAD_CFG_GPO(GPP_E17, 1, DEEP),
+	/* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */
+	PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
+	/* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */
+	PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
+	/* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_SOC_TX */
+	PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
+	/* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */
+	PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
+	/* E22 : DDPA_CTRLCLK ==> USB_C1_AUXP_DC: Retimer FW drives this pin */
+	PAD_NC(GPP_E22, NONE),
+	/* E23 : DDPA_CTRLDATA ==> USB_C1_AUXN_DC: Retimer FW drives this pin */
+	PAD_NC(GPP_E23, NONE),
+
+	/* F0  : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */
+	PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+	/* F1  : CNV_BRI_RSP ==> NCV_BRI_RSP */
+	PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
+	/* F2  : I2S2_TXD ==> CNV_RGI_DT_STRAP */
+	PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
+	/* F3  : I2S2_RXD ==> CNV_RGI_RSP */
+	PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
+	/* F4  : CNV_RF_RESET# ==> CNV_RF_RST_L */
+	PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+	/* F5  : MODEM_CLKREQ ==> CNV_CLKREQ0 */
+	PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
+	/* F6  : WWAN_CONFIG3 */
+	PAD_CFG_GPI(GPP_F6, NONE, DEEP),
+	/* F7  : EN_PP3300_TRACKPAD */
+	PAD_CFG_GPO(GPP_F7, 1, DEEP),
+	/* F8  : I2S_MCLK2_INOUT ==> NC */
+	PAD_NC(GPP_F8, NONE),
+	/* F9  : HP_INT_L */
+	PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, EDGE_BOTH),
+	/* F10 : EN_PP3300_TOUCHSCREEN */
+	PAD_CFG_GPO(GPP_F10, 0, DEEP),
+	/* F11 : PCH_GSPI1_FPMCU_CLK */
+	PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4),
+	/* F12 : PCH_GSPI1_FPMCU_MISO */
+	PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
+	/* F13 : PCH_GSPI1_FPMCU_MISO */
+	PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
+	/* F14 : WLAN_RST_ODL */
+	PAD_CFG_GPO(GPP_F14, 1, DEEP),
+	/* F15 : RCAM_RST_L */
+	PAD_CFG_GPO(GPP_F15, 1, DEEP),
+	/* F16 : PCH_GSPI1_FPMCU_CS_L */
+	PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4),
+	/* F17 : WWAN_RF_DISABLE_ODL */
+	PAD_CFG_GPO(GPP_F17, 1, DEEP),
+	/* F18 : WWAN_PCIE_WAKE_ODL */
+	PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE),
+	/* F19 : WLAN_INT_L */
+	PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE),
+	/* F20 : WWAN_RST_ODL */
+	PAD_CFG_GPO(GPP_F20, 1, DEEP),
+	/* F21 : WWAN_DPR_SAR_ODL */
+	PAD_CFG_GPO(GPP_F21, 1, DEEP),
+	/* F22 : VNN_CTRL */
+	PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+	/* F23 : V1P05_CTRL */
+	PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
+
+	/* H0  : GPPH0_BOOT_STRAP1 */
+	PAD_NC(GPP_H0, NONE),
+	/* H1  : GPPH1_BOOT_STRAP2 */
+	PAD_NC(GPP_H1, NONE),
+	/* H2  : GPPH2_BOOT_STRAP3 */
+	PAD_NC(GPP_H2, NONE),
+	/* H3 : SD_PERST_L */
+	PAD_CFG_GPO(GPP_H3, 1, DEEP),
+	/* H4 : PCH_I2C0_MISC_SCL */
+	PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+	/* H5 : PCH_I2C0_MISC_SDA */
+	PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+	/* H6 : PCH_I2C1_CAM_SDA */
+	PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+	/* H7 : PCH_I2C1_CAM_SCL */
+	PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+	/* H8 : WWAN_WLAN_COEX1 */
+	PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
+	/* H9 : WWAN_WLAN_COEX2 */
+	PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
+	/* H10 : UART_PCH_RX_DEBUG_TX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* H11 : UART_PCH_TX_DEBUG_RX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+	/* H12 : WWAN_CONFIG0 */
+	PAD_CFG_GPI(GPP_H12, NONE, DEEP),
+	/* H13 : RCAM_SNRPWR_EN */
+	PAD_CFG_GPO(GPP_H13, 0, DEEP),
+	/* H15 : DDPB_HDMI_CTRLCLK */
+	PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
+	/* H16 : DDPB_CTRLCLK ==> NC */
+	PAD_NC(GPP_H16, NONE),
+	/* H17 : DDPB_HDMI_CTRLDATA */
+	PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+	/* H18 : CPU_C10_GATE# ==> CPU_C10_GATE_L */
+	PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+	/* H19 : USB_C1_RT_FORCE_PWR */
+	PAD_CFG_GPO(GPP_H19, 1, DEEP),
+	/* H20 : EN_MIPI_RCAM_PWR */
+	PAD_CFG_GPO(GPP_H20, 0, DEEP),
+	/* H21 : CAM_MCLK1 */
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+	/* H22 : CAM_MCLK0 */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+	/* H23 : IMGCLKOUT4 ==> NC */
+	PAD_NC(GPP_H23, NONE),
+
+	/* R0 : I2S0_HP_SCLK */
+	PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
+	/* R1 : I2S0_HP_SFRM */
+	PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
+	/* R2 : I2S0_PCH_TX_HP_RX_STRAP */
+	PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
+	/* R3 : I2S0_PCH_RX_HP_TX */
+	PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
+	/* R4 : DMIC_CLK0 */
+	PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
+	/* R5 : DMIC_DATA0 */
+	PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
+	/* R6 : WWAN_WLAN_COEX3 */
+	PAD_CFG_NF(GPP_R6, NONE, DEEP, NF1),
+	/* R7 : SAR0_INT_L */
+	PAD_CFG_GPI_APIC(GPP_R7, NONE, PLTRST, LEVEL, NONE),
+
+
+	/* S0 : I2S1_SPKR_SCLK */
+	PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
+	/* S1 : I2S1_SPKR_SFRM */
+	PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
+	/* S2 : I2S1_PCH_TX_SPKR_RX */
+	PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
+	/* S3 : I2S1_PCH_TX_SPKR_RX */
+	PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4),
+	/* S5 : SPKR_INT_L */
+	PAD_CFG_GPI_APIC(GPP_S5, NONE, PLTRST, LEVEL, NONE),
+	/* S6 : DMIC_CLK1 */
+	PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
+	/* S7 : DMIC_DATA1 */
+	PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
+
+	/* GPD0: BATLOW# ==> BATLOW_L */
+	PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+	/* GPD1: ACPRESENT ==> PCH_ACPRESENT */
+	PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+	/* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */
+	PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
+	/* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */
+	PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
+	/* GPD4: SLP_S3# ==> SLP_S3_L */
+	PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+	/* GPD5: SLP_S4# ==> SLP_S4_L */
+	PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+	/* GPD6: SLP_A# ==> SLP_A_L */
+	PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+	/* GPD7: GPD7_STRAP */
+	PAD_CFG_GPI(GPD7, DN_20K, DEEP),
+	/* GPD8: SUSCLK ==> PCH_SUSCLK */
+	PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+	/* GPD9: SLP_WLAN_L */
+	PAD_CFG_NF(GPD9, NONE, DEEP, NF1),
+	/* GPD10: SLP_S5# ==> SLP_S5_L */
+	PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+	/* GPD11: LANPHYC ==> NC */
+	PAD_NC(GPD11, NONE),
+};
+
+const struct pad_config *__weak variant_base_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *__weak variant_override_gpio_table(size_t *num)
+{
+	*num = 0;
+	return NULL;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
+{
+	*num = ARRAY_SIZE(cros_gpios);
+	return cros_gpios;
+}
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/ec.h
new file mode 100644
index 0000000000..7dc957261b
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/ec.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MAINBOARD_EC_H__
+#define __MAINBOARD_EC_H__
+
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid, power button or mode change event */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+	(MAINBOARD_EC_S5_WAKE_EVENTS |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS	(MAINBOARD_EC_S3_WAKE_EVENTS)
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN	GPE_EC_WAKE
+
+/* Enable Tablet switch */
+#define EC_ENABLE_TBMC_DEVICE
+
+#define SIO_EC_MEMMAP_ENABLE	/* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE	/* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K	/* Enable PS/2 Keyboard */
+
+/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in variant/gpio.h */
+#define EC_ENABLE_SYNC_IRQ
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+
+#endif /* __MAINBOARD_EC_H__ */
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h
index 2f7e85085a..a145ac9859 100644
--- a/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h
@@ -12,6 +12,8 @@
  * The next set of functions return the gpio table and fill in the number of
  * entries for each table.
  */
+const struct pad_config *variant_base_gpio_table(size_t *num);
+const struct pad_config *variant_override_gpio_table(size_t *num);
 const struct cros_gpio *variant_cros_gpios(size_t *num);
 
 void variant_configure_early_gpio_pads(void);