diff options
| author | Subrata Banik <subratabanik@google.com> | 2022-01-03 18:07:13 +0000 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2022-01-16 13:33:14 +0000 |
| commit | a0d9ad322fe603d4d4cbccda9c7edcfbf0b13409 (patch) | |
| tree | 669b42cd23e87dd8dd89009173d820057afea520 /src/mainboard/intel | |
| parent | 98ce39dce48d9f4b88fb0d71af654f4ed948ea9b (diff) | |
soc/intel/skl: Replace dt `HeciEnabled` by `HECI1 disable` config
List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.
3. Make dt CSE PCI device `on` by default.
4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1
function disable at pre-boot instead of the dt policy that uses
`HeciEnabled = 0`.
Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/kblrvp/Kconfig | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/kunimitsu/Kconfig | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/kunimitsu/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/saddlebrook/Kconfig | 3 |
5 files changed, 9 insertions, 2 deletions
diff --git a/src/mainboard/intel/kblrvp/Kconfig b/src/mainboard/intel/kblrvp/Kconfig index 2abf8329f6..6b60ac46ea 100644 --- a/src/mainboard/intel/kblrvp/Kconfig +++ b/src/mainboard/intel/kblrvp/Kconfig @@ -31,6 +31,9 @@ config BOARD_INTEL_KBLRVP11 if BOARD_INTEL_KBLRVP_COMMON +config DISABLE_HECI1_AT_PRE_BOOT + default y + config VBOOT select VBOOT_LID_SWITCH diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index e17c8b71f3..bae6198118 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -20,7 +20,6 @@ chip soc/intel/skylake register "dptf_enable" = "1" # FSP Configuration - register "HeciEnabled" = "0" register "IoBufferOwnership" = "0" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index 85f9e54d82..22fffb0203 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -21,6 +21,9 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_SKYLAKE select HAVE_SPD_IN_CBFS +config DISABLE_HECI1_AT_PRE_BOOT + default y + config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_LID_SWITCH diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index ba4835eb25..deb9f38c7a 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -25,7 +25,6 @@ chip soc/intel/skylake register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" - register "HeciEnabled" = "0" register "SaGv" = "SaGv_Enabled" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch diff --git a/src/mainboard/intel/saddlebrook/Kconfig b/src/mainboard/intel/saddlebrook/Kconfig index decbb9688a..5d16d22875 100644 --- a/src/mainboard/intel/saddlebrook/Kconfig +++ b/src/mainboard/intel/saddlebrook/Kconfig @@ -16,6 +16,9 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_CMOS_DEFAULT select MAINBOARD_USES_IFD_GBE_REGION +config DISABLE_HECI1_AT_PRE_BOOT + default y + config MAINBOARD_DIR default "intel/saddlebrook" |