diff options
| author | Shuo Liu <shuo.liu@intel.com> | 2024-04-26 17:35:05 +0800 |
|---|---|---|
| committer | Lean Sheng Tan <sheng.tan@9elements.com> | 2024-05-02 17:43:42 +0000 |
| commit | a0aff6e15988f918b926c4cd222537d2f5a3f878 (patch) | |
| tree | 593424f7bba43c6b2361f305334c3ac8eac3f6e1 /src/mainboard/intel | |
| parent | b25fa1cf9ee3ea51c4c183d2d7f3d79c0bf8d573 (diff) | |
soc/intel/xeon_sp: Add get_cxl_mode
Configuration variable implementation (VPD, et al) is regarded to
be mainboard specific and should not be bounded to SoC codes.
Add get_cxl_mode so that SoC codes do not need to get this
configuration from VPD any more.
TEST=Build and boot on intel/archercity CRB with no significant log
differences
Change-Id: I1e08e92ad769112d7e570ee12cf973451a3befc0
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/archercity_crb/Makefile.mk | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/archercity_crb/util.c | 20 |
2 files changed, 22 insertions, 0 deletions
diff --git a/src/mainboard/intel/archercity_crb/Makefile.mk b/src/mainboard/intel/archercity_crb/Makefile.mk index 4c7a7beee1..b28d73c27a 100644 --- a/src/mainboard/intel/archercity_crb/Makefile.mk +++ b/src/mainboard/intel/archercity_crb/Makefile.mk @@ -2,5 +2,7 @@ bootblock-y += bootblock.c romstage-y += romstage.c +romstage-y += util.c ramstage-y += ramstage.c +ramstage-y += util.c CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/intel/archercity_crb/util.c b/src/mainboard/intel/archercity_crb/util.c new file mode 100644 index 0000000000..5197b23292 --- /dev/null +++ b/src/mainboard/intel/archercity_crb/util.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/ocp/include/vpd.h> +#include <soc/chip_common.h> +#include <soc/util.h> + +#if CONFIG(SOC_INTEL_HAS_CXL) +enum xeonsp_cxl_mode get_cxl_mode(void) +{ + int ocp_cxl_mode = get_cxl_mode_from_vpd(); + switch (ocp_cxl_mode) { + case CXL_SYSTEM_MEMORY: + return XEONSP_CXL_SYS_MEM; + case CXL_SPM: + return XEONSP_CXL_SP_MEM; + default: + return XEONSP_CXL_DISABLED; + } +} +#endif |