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authorPatrick Georgi <patrick@georgi-clan.de>2010-11-18 10:48:15 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2010-11-18 10:48:15 +0000
commit9e180387bdaf4ad6e29cd2b7044bccfb1b1e6f67 (patch)
tree5afbf2d9184c5ce68822150c6af1b3bb09419445 /src/mainboard/intel
parentd4917692ec81cb5a24a915a38a5a13837fadc619 (diff)
Move register block definitions out of board code into
chipset code (where it belongs) Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/eagleheights/romstage.c7
1 files changed, 1 insertions, 6 deletions
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 774f88f60f..07ba0a0bdf 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -41,16 +41,11 @@
#include "superio/intel/i3100/i3100_early_serial.c"
#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
#include "northbridge/intel/i3100/i3100.h"
+#include "southbridge/intel/i3100/i3100.h"
#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
-/* SATA */
-#define SATA_MAP 0x90
-
-#define SATA_MODE_IDE 0x00
-#define SATA_MODE_AHCI 0x01
-
#define RCBA_RPC 0x0224 /* 32 bit */
#define RCBA_TCTL 0x3000 /* 8 bit */