diff options
| author | Felix Singer <felixsinger@posteo.net> | 2021-07-12 16:19:53 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-07-13 18:47:00 +0000 |
| commit | 4dcac1304356fbc4e7c83d9eb024a0b0bde9f94e (patch) | |
| tree | 869cd67f41e09a351520cb6e3ad365bd1611aabd /src/mainboard/intel | |
| parent | 1be296c1e7f801d96cd078baea7dbe4ce01b4676 (diff) | |
intel/kblrvp: Move lockdown config to baseboard devicetree
Clean up lockdown configuration and move it to the baseboard's
devicetree.
Since most of the mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, use it
for the rvp8 variant for consistency as well.
Built intel/rvp11 with `BUILD_TIMELESS=1` and coreboot.rom remains
identical. intel/rvp8 changes, as expected.
Change-Id: I78e847c321c61c3a974b26f30bc2823ff84df651
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56212
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
4 files changed, 4 insertions, 15 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index e17c8b71f3..a5a51bf397 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -110,6 +110,10 @@ chip soc/intel/skylake # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index fa1367410b..bc4a677138 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -105,11 +105,6 @@ chip soc/intel/skylake .tdp_pl2_override = 60, }" - # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device domain 0 on device pci 04.0 off end # SA thermal subsystem device pci 17.0 on end # SATA diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 397155b789..b1d291722b 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -110,11 +110,6 @@ chip soc/intel/skylake [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ }" - # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device domain 0 on device pci 05.0 on end # SA IMGU device pci 14.3 on end # Camera diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index b677a343ac..83a86adb37 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -150,11 +150,6 @@ chip soc/intel/skylake # Use default SD card detect GPIO configuration register "sdcard_cd_gpio" = "GPP_G5" - # Lock Down - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - }" - device cpu_cluster 0 on device lapic 0 on end end |