mb/google,intel: Add ChromeOS GPIOs to onboard.h

Change-Id: Ia473596e3c9a75587cd1288c8816bfef66bef82e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

6 files changed, 40 insertions, 14 deletions

diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c
index b6c41640ac..d4408f4d06 100644
--- a/src/mainboard/intel/baskingridge/chromeos.c
+++ b/src/mainboard/intel/baskingridge/chromeos.c
@@ -7,12 +7,13 @@
 #include <southbridge/intel/common/gpio.h>
 #include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
+#include "onboard.h"
 
 void fill_lb_gpios(struct lb_gpios *gpios)
 {
 	struct lb_gpio chromeos_gpios[] = {
 		/* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */
-		{69, ACTIVE_HIGH, get_recovery_mode_switch(), "presence"},
+		{GPIO_REC_MODE, ACTIVE_HIGH, get_recovery_mode_switch(), "presence"},
 
 		/* Hard code the lid switch GPIO to open. */
 		{-1, ACTIVE_HIGH, 1, "lid"},
@@ -32,18 +33,18 @@ int get_recovery_mode_switch(void)
 	 * Recovery: GPIO69, Connected to J8E3, however the silkscreen says
 	 * J8E2. The jump is active high.
 	 */
-	return get_gpio(69);
+	return get_gpio(GPIO_REC_MODE);
 }
 
 int get_write_protect_state(void)
 {
 	/* Write protect is active low, so invert it here */
-	return !get_gpio(22);
+	return !get_gpio(GPIO_SPI_WP);
 }
 
 static const struct cros_gpio cros_gpios[] = {
-	CROS_GPIO_REC_AH(69, CROS_GPIO_DEVICE_NAME),
-	CROS_GPIO_WP_AL(22, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_REC_AH(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
 };
 
 void mainboard_chromeos_acpi_generate(void)
diff --git a/src/mainboard/intel/baskingridge/onboard.h b/src/mainboard/intel/baskingridge/onboard.h
new file mode 100644
index 0000000000..66812a55f0
--- /dev/null
+++ b/src/mainboard/intel/baskingridge/onboard.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef BASKINGRIDGE_ONBOARD_H
+#define BASKINGRIDGE_ONBOARD_H
+
+/* Recovery: GPIO69, active high - SV_DETECT - J8E3 (silkscreen: J8E2) */
+#define GPIO_REC_MODE	69
+
+/* Write protect is active low */
+#define GPIO_SPI_WP	22
+
+#endif
diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c
index 58732b11fb..2d0e2e1f44 100644
--- a/src/mainboard/intel/emeraldlake2/chromeos.c
+++ b/src/mainboard/intel/emeraldlake2/chromeos.c
@@ -7,12 +7,13 @@
 #include <southbridge/intel/common/gpio.h>
 #include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
+#include "onboard.h"
 
 void fill_lb_gpios(struct lb_gpios *gpios)
 {
 	struct lb_gpio chromeos_gpios[] = {
 		/* Recovery: GPIO22 */
-		{22, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"},
+		{GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), "presence"},
 
 		/* Hard code the lid switch GPIO to open. */
 		{-1, ACTIVE_HIGH, 1, "lid"},
@@ -29,18 +30,18 @@ void fill_lb_gpios(struct lb_gpios *gpios)
 int get_recovery_mode_switch(void)
 {
 	/* Recovery: GPIO22, active low */
-	return !get_gpio(22);
+	return !get_gpio(GPIO_REC_MODE);
 }
 
 int get_write_protect_state(void)
 {
 	/* Write protect is active low, so invert it here */
-	return !get_gpio(48);
+	return !get_gpio(GPIO_SPI_WP);
 }
 
 static const struct cros_gpio cros_gpios[] = {
-	CROS_GPIO_REC_AL(22, CROS_GPIO_DEVICE_NAME),
-	CROS_GPIO_WP_AL(48, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AL(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
 };
 
 void mainboard_chromeos_acpi_generate(void)
diff --git a/src/mainboard/intel/emeraldlake2/onboard.h b/src/mainboard/intel/emeraldlake2/onboard.h
new file mode 100644
index 0000000000..658ad83e19
--- /dev/null
+++ b/src/mainboard/intel/emeraldlake2/onboard.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef EMERALDLAKE2_ONBOARD_H
+#define EMERALDLAKE2_ONBOARD_H
+
+/* Recovery: GPIO22, active low */
+#define GPIO_REC_MODE	22
+
+/* Write protect is active low */
+#define GPIO_SPI_WP	48
+
+#endif
diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c
index 3f80b68034..91ce9aed27 100644
--- a/src/mainboard/intel/strago/chromeos.c
+++ b/src/mainboard/intel/strago/chromeos.c
@@ -6,10 +6,7 @@
 #include <types.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
-#define WP_GPIO	GP_E_22
-
-#define ACTIVE_LOW	0
-#define ACTIVE_HIGH	1
+#include "onboard.h"
 
 void fill_lb_gpios(struct lb_gpios *gpios)
 {
diff --git a/src/mainboard/intel/strago/onboard.h b/src/mainboard/intel/strago/onboard.h
index bc2e7a278a..d8af569733 100644
--- a/src/mainboard/intel/strago/onboard.h
+++ b/src/mainboard/intel/strago/onboard.h
@@ -29,6 +29,9 @@
 #define JACK_DETECT_GPIO_INDEX		95
 /* SCI: Gpio index in N bank */
 #define BOARD_SCI_GPIO_INDEX		15
+
+#define WP_GPIO				GP_E_22
+
 /* Trackpad: Gpio index in N bank */
 #define BOARD_TRACKPAD_GPIO_INDEX	18