mb/*: Update SPD mapping for sandybridge boards

Boards without HAVE_SPD_IN_CBFS: Move SPD mapping into devicetree.

Boards with HAVE_SPD_IN_CBFS: Convert to Haswell-style SPD mapping.

Change-Id: Id6ac0a36b2fc0b9686f6e875dd020ae8dba72a72
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>

7 files changed, 3 insertions, 34 deletions

diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb
index 37304f2167..f4e948f76c 100644
--- a/src/mainboard/intel/dcp847ske/devicetree.cb
+++ b/src/mainboard/intel/dcp847ske/devicetree.cb
@@ -13,6 +13,7 @@ chip northbridge/intel/sandybridge
 
 	# 1333MHz RAM frequency
 	register "max_mem_clock_mhz" = "666"
+	register "spd_addresses" = "{0x50, 0, 0x51, 0}"
 
 	register "usb_port_config" = "{
 		{1, 0, 0x0040},
diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c
index e2fd2aae9c..e0f27bab51 100644
--- a/src/mainboard/intel/dcp847ske/early_southbridge.c
+++ b/src/mainboard/intel/dcp847ske/early_southbridge.c
@@ -2,7 +2,6 @@
 
 #include <bootblock_common.h>
 #include <stdint.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 
 #include "superio.h"
@@ -126,12 +125,6 @@ void bootblock_mainboard_early_init(void)
 	hwm_init();
 }
 
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
-	read_spd(&spd[0], 0x50, id_only);
-	read_spd(&spd[2], 0x51, id_only);
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 #define USB_CONFIG(enabled, current, ocpin) { enabled, current, ocpin }
 #include "usb.h"
diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c
index d0decb4602..d9a6a9ebbb 100644
--- a/src/mainboard/intel/dcp847ske/romstage.c
+++ b/src/mainboard/intel/dcp847ske/romstage.c
@@ -2,13 +2,8 @@
 
 #include <stdint.h>
 #include <northbridge/intel/sandybridge/raminit.h>
-#include <southbridge/intel/bd82x6x/pch.h>
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
-	const uint8_t spdaddr[] = {0xa0, 0x00, 0xa2, 0x00};
-
-	memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
-
 	/* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
 }
diff --git a/src/mainboard/intel/dq67sw/devicetree.cb b/src/mainboard/intel/dq67sw/devicetree.cb
index 544a525b97..f29b772e8a 100644
--- a/src/mainboard/intel/dq67sw/devicetree.cb
+++ b/src/mainboard/intel/dq67sw/devicetree.cb
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 chip northbridge/intel/sandybridge
+	register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}"
 	device domain 0 on
 		subsystemid 0x8086 0x2008 inherit
 		device ref host_bridge on end	# Host bridge
diff --git a/src/mainboard/intel/dq67sw/early_init.c b/src/mainboard/intel/dq67sw/early_init.c
index 683dbf8f66..14317a69e0 100644
--- a/src/mainboard/intel/dq67sw/early_init.c
+++ b/src/mainboard/intel/dq67sw/early_init.c
@@ -1,7 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <bootblock_common.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <superio/winbond/w83667hg-a/w83667hg-a.h>
 #include <superio/winbond/common/winbond.h>
@@ -29,11 +28,3 @@ void bootblock_mainboard_early_init(void)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 }
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
-	read_spd(&spd[0], 0x50, id_only);
-	read_spd(&spd[1], 0x51, id_only);
-	read_spd(&spd[2], 0x52, id_only);
-	read_spd(&spd[3], 0x53, id_only);
-}
diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb
index a7f5d3bd3e..e75505e270 100644
--- a/src/mainboard/intel/emeraldlake2/devicetree.cb
+++ b/src/mainboard/intel/emeraldlake2/devicetree.cb
@@ -12,6 +12,7 @@ chip northbridge/intel/sandybridge
 	register "gpu_dp_b_hotplug" = "0x06"
 
 	register "max_mem_clock_mhz" = "800"
+	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
 
 	register "usb_port_config" = "{
 		{ 1, 0, 0x0040 },
diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c
index 853add4dd6..1974713520 100644
--- a/src/mainboard/intel/emeraldlake2/early_init.c
+++ b/src/mainboard/intel/emeraldlake2/early_init.c
@@ -1,15 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include <arch/hpet.h>
 #include <bootblock_common.h>
 #include <stdint.h>
 #include <arch/io.h>
 #include <superio/smsc/sio1007/sio1007.h>
-#include <northbridge/intel/sandybridge/sandybridge.h>
 #include <northbridge/intel/sandybridge/raminit.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
-#include <southbridge/intel/common/gpio.h>
 
 #define SIO_PORT 0x164e
 
@@ -50,9 +46,6 @@ void bootblock_mainboard_early_init(void)
 
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
-	const uint8_t spdaddr[] = { 0xa0, 0x00, 0xa4, 0x00 };
-
-	memcpy(pei_data->spd_addresses, &spdaddr, sizeof(pei_data->spd_addresses));
 }
 
 const struct southbridge_usb_port mainboard_usb_ports[] = {
@@ -72,9 +65,3 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 }, /* P12: Back port  (OC6) */
 	{ 1, 0, 5 }, /* P13: Back port  (OC5) */
 };
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
-	read_spd(&spd[0], 0x50, id_only);
-	read_spd(&spd[2], 0x52, id_only);
-}