diff options
| author | Nico Huber <nico.h@gmx.de> | 2024-01-12 16:22:19 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-19 13:18:17 +0000 |
| commit | 3d80d14cd4ed82e74057cea884dcb9bb7588c076 (patch) | |
| tree | 2b871fd211af0a239a0926f28c787e3cd406cc90 /src/mainboard/intel | |
| parent | 9bf38c7d672dbfe0771a15574a7e0c59f38c139c (diff) | |
soc/intel/jasperlake: Drop redundant PcieRpEnable
The PcieRpEnable option is redundant to our on/off setting in the
devicetrees. Let's use the common coreboot infrastructure instead.
Thanks to Nicholas for doing all the mainboard legwork!
Change-Id: Iea7f616f6db579c06722369c08de7cf7261dece8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79919
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb | 13 |
1 files changed, 1 insertions, 12 deletions
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 957ab1da72..59d69dc28f 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -63,11 +63,6 @@ chip soc/intel/jasperlake register "PchHdaAudioLinkDmicEnable[0]" = "1" register "PchHdaAudioLinkDmicEnable[1]" = "1" - # PCIe port 1 for M.2 E-key WLAN - # Enable Root Port 4(x4) for NVMe - register "PcieRpEnable[1]" = "1" - register "PcieRpEnable[4]" = "1" - # Enable ClkReqDetect 1 for WLAN # Enable ClkReqDetect 4 for NVMe register "PcieRpClkReqDetect[1]" = "1" @@ -469,14 +464,8 @@ chip soc/intel/jasperlake device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 off end # PCI Express Port 1 - device pci 1c.1 on end # PCI Express Port 2 - WLAN - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.1 on end # PCI Express Port 2 - M.2 E-key WLAN device pci 1c.4 on end # PCI Express Port 5 - NVMe - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 device pci 1e.0 on end # UART #0 device pci 1e.1 off end # UART #1 device pci 1e.2 off end # GSPI #0 |