diff options
| author | Bora Guvendik <bora.guvendik@intel.com> | 2021-05-17 18:19:22 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-30 20:18:42 +0000 |
| commit | 3585dc5be4ddf01ee61907d963e070386d31d054 (patch) | |
| tree | 157060641c208c26ba1444f00d5118ed446096d3 /src/mainboard/intel | |
| parent | fcb6a8034980cf925e40b6cea406884926a54361 (diff) | |
mb/intel/adlrvp_m: add ec device entry to devicetree
TEST=Boot to OS and verify acpi tables.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I3c78ac44afa3515acef9ea2d59f22f95e6b45e90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54490
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com>
Reviewed-by: John Zhao <john.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb index 80450e7cd4..68a1bfa1d6 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_m_ext_ec/overridetree.cb @@ -1,5 +1,12 @@ chip soc/intel/alderlake device domain 0 on + device pci 1f.0 on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end # eSPI device pci 1f.2 hidden # The pmc_mux chip driver is a placeholder for the |