diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2021-02-15 21:48:51 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-02-17 06:04:11 +0000 |
| commit | d93a5bc1150726b637f398df2ea2d1da1f47627e (patch) | |
| tree | c78f63f183b1f20bd5596beaecd0d84ae7da6fc0 /src/mainboard/intel | |
| parent | a7adf77afe88b2bfe0aaf6099462cc020c697814 (diff) | |
mb/intel/adlrvp: Fix incorrect SPD address issue on DDR4/DDR5
Assign 7-bit address of the targeted slave SPD.
TEST=Able to read correct SPD data from SMBUS.
Change-Id: If24e61b583638be7c055541c6eb126da28b542f6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/adlrvp/romstage_fsp_params.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 8a179d6d5b..c95d469a7c 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -39,12 +39,12 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) .topo = MEM_TOPO_DIMM_MODULE, .smbus = { [0] = { - .addr_dimm[0] = 0xa0, - .addr_dimm[1] = 0xa2, + .addr_dimm[0] = 0x50, + .addr_dimm[1] = 0x51, }, [1] = { - .addr_dimm[0] = 0xa4, - .addr_dimm[1] = 0xa6, + .addr_dimm[0] = 0x52, + .addr_dimm[1] = 0x53, }, }, }; |