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| author | Jonathan Neuschäfer <j.neuschaefer@gmx.net> | 2016-06-10 19:35:16 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-12 12:43:37 +0200 |
| commit | d15e9aaa48d4382de827522c1020edc63fb135f2 (patch) | |
| tree | 65b1a1efcfd6ab64ff8253fc3adacce07f5d1140 /src/mainboard/intel | |
| parent | 1282b8d99692ddfff5b78b03938b9b3555b17c00 (diff) | |
riscv-spike: Replace custom UART with a memory-mapped 8250
Since the HTIF is a non-standard interface, and coreboot already has a
8250 driver, I started implementing an 8250 core for spike[1].
[1]: https://github.com/riscv/riscv-isa-sim/pull/53
Change-Id: I84adc1169474baa8cc5837358a8ad3d184cfa51b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/15150
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/intel')
0 files changed, 0 insertions, 0 deletions