x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer

On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.

Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)

8 files changed, 14 insertions, 14 deletions

diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c
index 7aea6b6eae..e1bdb30bda 100644
--- a/src/mainboard/intel/baskingridge/romstage.c
+++ b/src/mainboard/intel/baskingridge/romstage.c
@@ -71,15 +71,15 @@ void mainboard_romstage_entry(unsigned long bist)
 {
 	struct pei_data pei_data = {
 		.pei_version = PEI_VERSION,
-		.mchbar = DEFAULT_MCHBAR,
-		.dmibar = DEFAULT_DMIBAR,
+		.mchbar = (uintptr_t)DEFAULT_MCHBAR,
+		.dmibar = (uintptr_t)DEFAULT_DMIBAR,
 		.epbar = DEFAULT_EPBAR,
 		.pciexbar = DEFAULT_PCIEXBAR,
 		.smbusbar = SMBUS_IO_BASE,
 		.wdbbar = 0x4000000,
 		.wdbsize = 0x1000,
 		.hpet_address = HPET_ADDR,
-		.rcba = DEFAULT_RCBA,
+		.rcba = (uintptr_t)DEFAULT_RCBA,
 		.pmbase = DEFAULT_PMBASE,
 		.gpiobase = DEFAULT_GPIOBASE,
 		.temp_mmio_base = 0xfed08000,
diff --git a/src/mainboard/intel/d945gclf/mptable.c b/src/mainboard/intel/d945gclf/mptable.c
index b0360bfe08..ee05919e6d 100644
--- a/src/mainboard/intel/d945gclf/mptable.c
+++ b/src/mainboard/intel/d945gclf/mptable.c
@@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v)
 	mptable_write_buses(mc, NULL, &isa_bus);
 
 	/* I/O APICs:	APIC ID	Version	State		Address */
-	smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+	smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
 
 	/* Legacy Interrupts */
 
diff --git a/src/mainboard/intel/eagleheights/mptable.c b/src/mainboard/intel/eagleheights/mptable.c
index 809feec9de..b9c2fc3cf3 100644
--- a/src/mainboard/intel/eagleheights/mptable.c
+++ b/src/mainboard/intel/eagleheights/mptable.c
@@ -67,14 +67,14 @@ static void *smp_write_config_table(void *v)
 	uint32_t pin, route;
 	device_t dev;
 	struct resource *res;
-	unsigned long rcba;
+	u8 *rcba;
 
 	dev = dev_find_slot(0, PCI_DEVFN(0x1F,0));
 	res = find_resource(dev, RCBA);
 	if (!res) {
 	  return NULL;
 	}
-	rcba = res->base;
+	rcba = res2mmio(res, 0, 0);
 
         mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
 
@@ -121,7 +121,7 @@ static void *smp_write_config_table(void *v)
 	mptable_write_buses(mc, NULL, &bus_isa);
 
 	/*I/O APICs: APIC ID Version State Address*/
-	smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
+	smp_write_ioapic(mc, 2, 0x20, VIO_APIC_VADDR);
 
 	mptable_add_isa_interrupts(mc, bus_isa, IO_APIC0, 0);
 
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 5700162112..a45ef7e566 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -83,7 +83,7 @@ static void early_config(void)
 	u32 gcs, rpc, fd;
 
 	/* Enable RCBA */
-	pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
+	pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1);
 
 	/* Disable watchdog */
 	gcs = read32(DEFAULT_RCBA + RCBA_GCS);
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index adcf175d04..45d92d898c 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -135,15 +135,15 @@ void main(unsigned long bist)
 
 	struct pei_data pei_data = {
 		.pei_version = PEI_VERSION,
-		.mchbar = DEFAULT_MCHBAR,
-		.dmibar = DEFAULT_DMIBAR,
+		.mchbar = (uintptr_t)DEFAULT_MCHBAR,
+		.dmibar = (uintptr_t)DEFAULT_DMIBAR,
 		.epbar = DEFAULT_EPBAR,
 		.pciexbar = CONFIG_MMCONF_BASE_ADDRESS,
 		.smbusbar = SMBUS_IO_BASE,
 		.wdbbar = 0x4000000,
 		.wdbsize = 0x1000,
 		.hpet_address = CONFIG_HPET_ADDRESS,
-		.rcba = DEFAULT_RCBABASE,
+		.rcba = (uintptr_t)DEFAULT_RCBABASE,
 		.pmbase = DEFAULT_PMBASE,
 		.gpiobase = DEFAULT_GPIOBASE,
 		.thermalbase = 0xfed08000,
diff --git a/src/mainboard/intel/mohonpeak/romstage.c b/src/mainboard/intel/mohonpeak/romstage.c
index ba5091ab51..e06682ccd8 100644
--- a/src/mainboard/intel/mohonpeak/romstage.c
+++ b/src/mainboard/intel/mohonpeak/romstage.c
@@ -32,7 +32,7 @@
 
 static void interrupt_routing_config(void)
 {
-	u32 ilb_base = pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf;
+	u8 *ilb_base = (u8 *)(pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf);
 
 	/*
 	* Initialize Interrupt Routings for each device in ilb_base_address.
diff --git a/src/mainboard/intel/mtarvon/mptable.c b/src/mainboard/intel/mtarvon/mptable.c
index 4dd13f9279..fa07fd7155 100644
--- a/src/mainboard/intel/mtarvon/mptable.c
+++ b/src/mainboard/intel/mtarvon/mptable.c
@@ -42,7 +42,7 @@ static void *smp_write_config_table(void *v)
 	mptable_write_buses(mc, NULL, &bus_isa);
 
 	/* IOAPIC handling */
-	smp_write_ioapic(mc, 0x01, 0x20, IO_APIC_ADDR);
+	smp_write_ioapic(mc, 0x01, 0x20, VIO_APIC_VADDR);
 
 	mptable_add_isa_interrupts(mc, bus_isa, 0x1, 0);
 
diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c
index 9ad6ea6d6e..87b40dd525 100644
--- a/src/mainboard/intel/truxton/mptable.c
+++ b/src/mainboard/intel/truxton/mptable.c
@@ -70,7 +70,7 @@ static void *smp_write_config_table(void *v)
 	mptable_write_buses(mc, NULL, &bus_isa);
 
 	/* IOAPIC handling */
-	smp_write_ioapic(mc, 0x8, 0x20, IO_APIC_ADDR);
+	smp_write_ioapic(mc, 0x8, 0x20, VIO_APIC_VADDR);
 
 	mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0);