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authorSubrata Banik <subrata.banik@intel.com>2021-01-27 12:50:06 +0530
committerPatrick Georgi <pgeorgi@google.com>2021-01-28 09:26:48 +0000
commitac8c357ddcf2c58c4903c198224b13f045672ca4 (patch)
tree370b0d132a080314128a37400c487ffad3246646 /src/mainboard/intel
parent316466b76513dad87f1b7c90eab142ddea955fcc (diff)
mb/intel/adlrvp: Configure SATA DEVSLP as per latest schematics
1. GPP_E5 => Remove unused GPIOs 2. GPP_H12, GPP_H13 => Program the correct Native Functions for GPIO Change-Id: I588a8c1153eaa1bf818a081c6c5d18a669017d95 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49964 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/adlrvp/gpio.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c
index 3131cc0c05..1996683778 100644
--- a/src/mainboard/intel/adlrvp/gpio.c
+++ b/src/mainboard/intel/adlrvp/gpio.c
@@ -226,10 +226,9 @@ static const struct pad_config gpio_table[] = {
/* SMB_DATA */
PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
- /* SATADevSlpPin to GPIO pin mapping */
- PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
- /* SATA DIRECT DEVSLP*/
- PAD_CFG_NF(GPP_H12, NONE, DEEP, NF5),
+ /* SATA DEVSLP */
+ PAD_CFG_NF(GPP_H12, NONE, DEEP, NF4),
+ PAD_CFG_NF(GPP_H13, NONE, DEEP, NF5),
/* SATA LED pin */
PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1),