summaryrefslogtreecommitdiff
path: root/src/mainboard/intel
diff options
context:
space:
mode:
authorArthur Heymans <arthur@aheymans.xyz>2017-09-22 12:30:54 +0200
committerArthur Heymans <arthur@aheymans.xyz>2017-09-23 22:29:35 +0000
commit8b64e7ae21f2042f837f3af222754e1e8ef5b3d6 (patch)
tree0451ec227251a8bc2261ca54bbf2082088c56c10 /src/mainboard/intel
parentb47444533bf9593b87e5bfc938361817e56300f5 (diff)
mb/intel/dg43gt: Add romstage timestamps
Change-Id: I0383dd9b582d5c77be66ecd74bcf1a438f874cc7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/dg43gt/romstage.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c
index 5b9816345d..6944b1819e 100644
--- a/src/mainboard/intel/dg43gt/romstage.c
+++ b/src/mainboard/intel/dg43gt/romstage.c
@@ -25,6 +25,7 @@
#include <superio/winbond/common/winbond.h>
#include <lib.h>
#include <northbridge/intel/x4x/iomap.h>
+#include <timestamp.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
#define LPC_DEV PCI_DEV(0, 0x1f, 0)
@@ -71,6 +72,9 @@ void mainboard_romstage_entry(unsigned long bist)
u8 boot_path = 0;
u8 s3_resume;
+ timestamp_init(get_initial_timestamp());
+ timestamp_add_now(TS_START_ROMSTAGE);
+
/* Disable watchdog timer */
RCBA32(0x3410) = RCBA32(0x3410) | 0x20;
@@ -93,7 +97,9 @@ void mainboard_romstage_entry(unsigned long bist)
boot_path = BOOT_PATH_WARM_RESET;
printk(BIOS_DEBUG, "Initializing memory\n");
+ timestamp_add_now(TS_BEFORE_INITRAM);
sdram_initialize(boot_path, spd_addrmap);
+ timestamp_add_now(TS_AFTER_INITRAM);
quick_ram_check();
printk(BIOS_DEBUG, "Memory initialized\n");