diff options
| author | Wisley Chen <wisley.chen@quantatw.com> | 2016-12-23 04:43:18 -0500 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-01-03 16:54:09 +0100 |
| commit | 83560cf004ac25d3386599b9b446eb0794989a83 (patch) | |
| tree | 00835f30b84dfcff66f0690300d5448873f345ea /src/mainboard/intel | |
| parent | 0984d1da43dae419695041d9792fa96da91b42aa (diff) | |
google/snappy: Update DPTF settings
1. Update DPTF TSR1/TSR2 passive/critial trigger points.
TSR1 passive point:53, critial point:80
TSR2 passive point:90, critial point:100
2. Update PL1 Min to 4W and PL1 Max to 12W
3. Update thermal relationship table (TRT) setting.
BUG=none
BRANCH=master
TEST=build, boot on snappy dut and verified by thermal team member.
Change-Id: I8b4fb178daa7c2e4091a14779a125bd5e943d023
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17955
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
0 files changed, 0 insertions, 0 deletions