diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-07-05 19:13:15 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-07-09 12:44:26 +0000 |
| commit | 8104effa0dc25bac4693e8d76c1e10039dd47bad (patch) | |
| tree | edc8e60e8acc569b90df57145458801ff670d403 /src/mainboard/intel | |
| parent | 96dec04207604fdd58ab2f76f8667542c03902e4 (diff) | |
mainboard/intel/tglrvp: Remove unused PrmrrSize chip config
Refer to commit 7736bfc
TEST=Able to build and boot TGLRVP.
Change-Id: Ie9a97cee7d7793077167db3a642dcbca45b09427
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43139
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 2 |
2 files changed, 0 insertions, 4 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 401077229a..1396d3ac82 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -38,8 +38,6 @@ chip soc/intel/tigerlake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - register "PrmrrSize" = "0x10000000" - register "PcieRpEnable[2]" = "1" register "PcieRpEnable[3]" = "1" register "PcieRpEnable[8]" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index d095ff39c9..c3e41a2644 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -38,8 +38,6 @@ chip soc/intel/tigerlake # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" - register "PrmrrSize" = "0x10000000" - register "PcieRpEnable[2]" = "1" register "PcieRpEnable[3]" = "1" register "PcieRpEnable[8]" = "1" |