Intel i82810 boards & chips: Remove - using LATE_CBMEM_INIT

All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.

If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.

chips:
northbridge/intel/i82810

Mainboards:
src/mainboard/asus/mew-am
src/mainboard/asus/mew-vm
src/mainboard/ecs/p6iwp-fe
src/mainboard/hp/e_vectra_p2706t
src/mainboard/intel/d810e2cb
src/mainboard/mitac/6513wu
src/mainboard/msi/ms6178
src/mainboard/nec/powermate2000

Change-Id: Ib273316c59f499e6cd3a0e4c4dc4c2cce94ff291
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/23300
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 0 insertions, 430 deletions

diff --git a/src/mainboard/intel/d810e2cb/Kconfig b/src/mainboard/intel/d810e2cb/Kconfig
deleted file mode 100644
index 8695da962c..0000000000
--- a/src/mainboard/intel/d810e2cb/Kconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-if BOARD_INTEL_D810E2CB
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_INTEL_SOCKET_FC_PGA370
-	select NORTHBRIDGE_INTEL_I82810
-	select SOUTHBRIDGE_INTEL_I82801BX
-	select SUPERIO_SMSC_SMSCSUPERIO
-	select HAVE_PIRQ_TABLE
-	select USE_WATCHDOG_ON_BOOT
-	select BOARD_ROMSIZE_KB_512
-
-config MAINBOARD_DIR
-	string
-	default intel/d810e2cb
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "D810E2CB"
-
-config IRQ_SLOT_COUNT
-	int
-	default 7
-
-endif # BOARD_INTEL_D810E2CB
diff --git a/src/mainboard/intel/d810e2cb/Kconfig.name b/src/mainboard/intel/d810e2cb/Kconfig.name
deleted file mode 100644
index 8bf8624ab8..0000000000
--- a/src/mainboard/intel/d810e2cb/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_INTEL_D810E2CB
-	bool "D810E2CB"
diff --git a/src/mainboard/intel/d810e2cb/board_info.txt b/src/mainboard/intel/d810e2cb/board_info.txt
deleted file mode 100644
index cc1327cd82..0000000000
--- a/src/mainboard/intel/d810e2cb/board_info.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-Category: desktop
-Board URL: http://downloadcenter.intel.com/Detail_Desc.aspx?agr=Y&DwnldID=17789&lang=eng&wapkw=d810e2cb
-ROM package: PLCC
-ROM protocol: FWH
-ROM socketed: n
-Release year: 1999
diff --git a/src/mainboard/intel/d810e2cb/devicetree.cb b/src/mainboard/intel/d810e2cb/devicetree.cb
deleted file mode 100644
index 461a357a40..0000000000
--- a/src/mainboard/intel/d810e2cb/devicetree.cb
+++ /dev/null
@@ -1,78 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; either version 2 of the License, or
-## (at your option) any later version.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-chip northbridge/intel/i82810           # Northbridge
-  device cpu_cluster 0 on              # APIC cluster
-    chip cpu/intel/socket_FC_PGA370      # CPU
-      device lapic 0 on end              # APIC
-    end
-  end
-  device domain 0 on                # PCI domain
-    device pci 0.0 on end               # Graphics Memory Controller Hub (GMCH)
-    device pci 1.0 on end		# Chipset Graphics Controller (CGC)
-    chip southbridge/intel/i82801bx     # Southbridge
-      register "pirqa_routing" = "0x05"
-      register "pirqb_routing" = "0x06"
-      register "pirqc_routing" = "0x07"
-      register "pirqd_routing" = "0x09"
-      register "pirqe_routing" = "0x0a"
-      register "pirqf_routing" = "0x80"
-      register "pirqg_routing" = "0x80"
-      register "pirqh_routing" = "0x0b"
-
-      register "ide0_enable" = "1"
-      register "ide1_enable" = "1"
-
-      device pci 1e.0 on end		# PCI bridge
-      device pci 1f.0 on                # ISA bridge
-        chip superio/smsc/smscsuperio   # Super I/O (SMSC LPC47M102)
-          device pnp 4e.0 on            # Floppy
-            io 0x60 = 0x3f0
-            irq 0x70 = 6
-            drq 0x74 = 2
-          end
-          device pnp 4e.3 on            # Parallel port
-            io 0x60 = 0x378
-            irq 0x70 = 7
-            drq 0x74 = 4
-          end
-          device pnp 4e.4 on            # COM1
-            io 0x60 = 0x3f8
-            irq 0x70 = 4
-          end
-          device pnp 4e.5 off end       # COM2
-          device pnp 4e.7 on            # PS/2 keyboard / mouse
-            io 0x60 = 0x60
-            io 0x62 = 0x64
-            irq 0x70 = 1                # PS/2 keyboard interrupt
-            irq 0x72 = 12               # PS/2 mouse interrupt
-          end
-          device pnp 4e.9 off end       # Game port
-          device pnp 4e.a on            # Runtime registers
-            io 0x60 = 0x800
-          end
-          device pnp 4e.b off end       # MPU-401
-        end
-      end
-      device pci 1f.1 on end            # IDE
-      device pci 1f.2 on end            # USB
-      device pci 1f.3 on end            # SMbus
-      device pci 1f.4 on end            # USB
-      device pci 1f.5 on end            # Audio controller
-      device pci 1f.6 off end           # Modem controller
-    end
-  end
-end
diff --git a/src/mainboard/intel/d810e2cb/gpio.c b/src/mainboard/intel/d810e2cb/gpio.c
deleted file mode 100644
index 84e49d69a6..0000000000
--- a/src/mainboard/intel/d810e2cb/gpio.c
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <delay.h>
-
-#define PME_DEV			PNP_DEV(0x4e, 0x0a)
-#define PME_IO_BASE_ADDR	0x800      /* Runtime register base address */
-
-/* Early mainboard specific GPIO setup. */
-static void mb_gpio_init(void)
-{
-	device_t dev;
-	uint16_t port;
-
-	/* Southbridge GPIOs. */
-	/* Set the LPC device statically. */
-	dev = PCI_DEV(0x0, 0x1f, 0x0);
-
-	/* Set the value for GPIO base address register and enable GPIO. */
-	pci_write_config32(dev, GPIO_BASE, (GPIO_BASE_ADDR | 1));
-	pci_write_config8(dev, GPIO_CNTL, 0x10);
-
-	udelay(10);
-	outl(0x1a203180, GPIO_BASE_ADDR + 0x00); /* GPIO_USE_SEL */
-	outl(0x0000ffff, GPIO_BASE_ADDR + 0x04); /* GP_IO_SEL */
-	outl(0x13bf0000, GPIO_BASE_ADDR + 0x0c); /* GP_LVL */
-	outl(0x00040000, GPIO_BASE_ADDR + 0x18); /* GPO_BLINK */
-	outl(0x000039ff, GPIO_BASE_ADDR + 0x2c); /* GPI_INV */
-
-	/* Super I/O GPIOs. */
-	dev = PME_DEV;
-	port = dev >> 8;
-
-	/* Enter the configuration state. */
-	outb(0x55, port);
-	pnp_set_logical_device(dev);
-	pnp_set_enable(dev, 0);
-	pnp_set_iobase(dev, PNP_IDX_IO0, PME_IO_BASE_ADDR);
-	pnp_set_enable(dev, 1);
-
-	/* GP10 - J1B1 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x23);
-
-	/* GP11 - J1B2 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x24);
-
-	/* GP12 - J2B1 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x25);
-
-	/* GP13 - J2B2 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x26);
-
-	/* GP14 - J1X */
-	outl(0x01, PME_IO_BASE_ADDR + 0x27);
-
-	/* GP15 - J1Y */
-	outl(0x01, PME_IO_BASE_ADDR + 0x28);
-
-	/* GP16 - J2X */
-	outl(0x01, PME_IO_BASE_ADDR + 0x29);
-
-	/* GP17 - J2Y */
-	outl(0x01, PME_IO_BASE_ADDR + 0x2a);
-
-	/* GP20 - 8042 P17 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x2b);
-
-	/* GP21 - 8042 P16 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x2c);
-
-	/* GP22 - 8042 P12 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x2d);
-
-	/* GP24 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x2f);
-
-	/* GP25 - MIDI_IN */
-	outl(0x01, PME_IO_BASE_ADDR + 0x30);
-
-	/* GP26 - MIDI_OUT */
-	outl(0x01, PME_IO_BASE_ADDR + 0x31);
-
-	/* GP27 - nIO_SMI */
-	outl(0x04, PME_IO_BASE_ADDR + 0x32);
-
-	/* GP30 - FAN_TACH2 */
-	outl(0x05, PME_IO_BASE_ADDR + 0x33);
-
-	/* GP31 - FAN_TACH1 */
-	outl(0x05, PME_IO_BASE_ADDR + 0x34);
-
-	/* GP32 - FAN2 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x35);
-
-	/* GP33 - FAN1 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x36);
-
-	/* GP34 - IRRX2 */
-	outl(0x05, PME_IO_BASE_ADDR + 0x37);
-
-	/* GP35 - IRTX2 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x38);
-
-	/* GP36 - nKBDRST */
-	outl(0x84, PME_IO_BASE_ADDR + 0x39);
-
-	/* GP37 - A20M */
-	outl(0x84, PME_IO_BASE_ADDR + 0x3a);
-
-	/* GP40 - DRVDEN0 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x3b);
-
-	/* GP41 - DRVDEN1 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x3c);
-
-	/* GP42 - nIO_PME */
-	outl(0x84, PME_IO_BASE_ADDR + 0x3d);
-
-	/* GP43 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x3e);
-
-	/* GP50 - nIR2 */
-	outl(0x05, PME_IO_BASE_ADDR + 0x3f);
-
-	/* GP51 - nDCD2 */
-	outl(0x05, PME_IO_BASE_ADDR + 0x40);
-
-	/* GP52 - RXD2 */
-	outl(0x05, PME_IO_BASE_ADDR + 0x41);
-
-	/* GP53 - TXD2 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x42);
-
-	/* GP54 - nDSR2 */
-	outl(0x05, PME_IO_BASE_ADDR + 0x43);
-
-	/* GP55 - nRTS2 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x44);
-
-	/* GP56 - nCTS2 */
-	outl(0x05, PME_IO_BASE_ADDR + 0x45);
-
-	/* GP57 - nDTR2 */
-	outl(0x04, PME_IO_BASE_ADDR + 0x46);
-
-	/* GP60 - LED1 */
-	outl(0x84, PME_IO_BASE_ADDR + 0x47);
-
-	/* GP61 - LED2 */
-	outl(0x84, PME_IO_BASE_ADDR + 0x48);
-
-	/* GP1 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x4b);
-
-	/* GP2 */
-	outl(0x14, PME_IO_BASE_ADDR + 0x4c);
-
-	/* GP3 */
-	outl(0xda, PME_IO_BASE_ADDR + 0x4d);
-
-	/* GP4 */
-	outl(0x08, PME_IO_BASE_ADDR + 0x4e);
-
-	/* GP5 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x4f);
-
-	/* GP6 */
-	outl(0x00, PME_IO_BASE_ADDR + 0x50);
-
-	/* FAN1 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x56);
-
-	/* FAN2 */
-	outl(0x01, PME_IO_BASE_ADDR + 0x57);
-
-	/* Fan Control */
-	outl(0xf0, PME_IO_BASE_ADDR + 0x58);
-
-	/* Fan1 Preload */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5b);
-
-	/* Fan2 Preload */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5c);
-
-	/* LED1 */
-	outl(0x03, PME_IO_BASE_ADDR + 0x5d);
-
-	/* LED2 */
-	outl(0x03, PME_IO_BASE_ADDR + 0x5e);
-
-	/* Keyboard Scan Code */
-	outl(0x00, PME_IO_BASE_ADDR + 0x5f);
-
-	/* Exit the configuration state. */
-	outb(0xaa, port);
-}
diff --git a/src/mainboard/intel/d810e2cb/irq_tables.c b/src/mainboard/intel/d810e2cb/irq_tables.c
deleted file mode 100644
index 7d4de66c1e..0000000000
--- a/src/mainboard/intel/d810e2cb/irq_tables.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/pirq_routing.h>
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,		/* u32 signature */
-	PIRQ_VERSION,		/* u16 version */
-	32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus (7)*/
-	0x00,			/* Interrupt router bus */
-	(0x1f << 3) | 0x0,	/* Interrupt router dev */
-	0,			/* IRQs devoted exclusively to PCI usage */
-	0x8086,			/* Vendor */
-	0x2440,			/* Device */
-	0,			/* Miniport */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0xd9,			/* Checksum (has to be set to some value that
-				 * would give 0 after the sum of all bytes
-				 * for this structure (including checksum).
-				 */
-	{
-		/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
-		{0x00, (0x00 << 3) | 0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-		{0x00, (0x01 << 3) | 0x0, {{0x60, 0xdeb8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-		{0x00, (0x1e << 3) | 0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-		{0x00, (0x1f << 3) | 0x0, {{0x60, 0xdef8}, {0x61, 0xdef8}, {0x6b, 0xdef8}, {0x63, 0xdef8}}, 0x0, 0x0},
-		{0x01, (0x01 << 3) | 0x0, {{0x62, 0xdef8}, {0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}}, 0x1, 0x0},
-		{0x01, (0x02 << 3) | 0x0, {{0x63, 0xdef8}, {0x60, 0xdef8}, {0x61, 0xdef8}, {0x62, 0xdef8}}, 0x2, 0x0},
-		{0x01, (0x08 << 3) | 0x0, {{0x68, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/intel/d810e2cb/romstage.c b/src/mainboard/intel/d810e2cb/romstage.c
deleted file mode 100644
index 5bcee0c544..0000000000
--- a/src/mainboard/intel/d810e2cb/romstage.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2010 Joseph Smith <joe@settoplinux.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <console/console.h>
-#include <southbridge/intel/i82801bx/i82801bx.h>
-#include <northbridge/intel/i82810/raminit.h>
-#include <cpu/x86/bist.h>
-#include <cpu/intel/romstage.h>
-#include <superio/smsc/smscsuperio/smscsuperio.h>
-#include "gpio.c"
-#include <lib.h>
-
-#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
-
-void mainboard_romstage_entry(unsigned long bist)
-{
-	/* Set southbridge and Super I/O GPIOs. */
-	mb_gpio_init();
-
-	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-	console_init();
-
-	report_bist_failure(bist);
-	enable_smbus();
-	dump_spd_registers();
-	sdram_set_registers();
-	sdram_set_spd_registers();
-	sdram_enable();
-}