diff options
| author | Furquan Shaikh <furquan@google.com> | 2021-08-24 13:47:00 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2021-09-13 22:43:19 +0000 |
| commit | ecc459301f54d412bba67507e7e9fbac1834f0c2 (patch) | |
| tree | 2ff3bf80ba658a6f7b0c919f04d1e172d825db8f /src/mainboard/intel | |
| parent | 2306ee36f04aa79dd1064ee6b5841b20e21b7fde (diff) | |
mb/intel/tglrvp: Enable USB4 resources using SoC Kconfig
This change uses the newly added `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES`
Kconfig to enable USB4 resources and drops the configuration
in mainboard.
Change-Id: I707c5d63ea8c58e72126fe0d319ba81a99221ba5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/tglrvp/Kconfig | 16 |
1 files changed, 1 insertions, 15 deletions
diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig index 117343596e..2c4c48a438 100644 --- a/src/mainboard/intel/tglrvp/Kconfig +++ b/src/mainboard/intel/tglrvp/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_CSE_LITE_SKU select MAINBOARD_HAS_TPM2 select MAINBOARD_HAS_SPI_TPM_CR50 + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES select SPI_TPM config CHROMEOS @@ -53,21 +54,6 @@ config MAINBOARD_FAMILY string default "Intel_tglrvp" -config PCIEXP_HOTPLUG - default y - -config PCIEXP_HOTPLUG_BUSES - int - default 42 - -config PCIEXP_HOTPLUG_MEM - hex - default 0xc200000 # 194 MiB - -config PCIEXP_HOTPLUG_PREFETCH_MEM - hex - default 0x1c00000 # 448 MiB - config DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" |