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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-06-08 14:01:05 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-06-11 19:17:49 +0200 |
| commit | db601b68182df47a28b106ba07e97f222ff39140 (patch) | |
| tree | 419252101679bb5b6aa7ae2900f0db93abb79ef2 /src/mainboard/intel | |
| parent | d131ea30785d0d862e169135a9d4c24afaeaa8c0 (diff) | |
mainboard/intel/galileo: Support bootblock in C
Initialize the GPIOs during the boot block to properly route the SOC
UART pins.
TEST=Build and run on Galileo Gen2
Change-Id: I22c24f8c83f04566a0bbd598a141a5209569a924
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15133
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/galileo/Makefile.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index 83fb0db3bc..5aad30861a 100644 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -17,6 +17,9 @@ ifeq ($(CONFIG_PLATFORM_USES_FSP1_1),y) CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark endif +bootblock-y += gpio.c +bootblock-y += reg_access.c + romstage-y += gpio.c romstage-y += reg_access.c |