diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-10 18:22:11 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-10 18:22:11 +0000 |
| commit | d1a1d57adca92dd71f62dfb9363def532c3fc0e6 (patch) | |
| tree | b79e7be2c1f36d33edd04b5e4a0ec96d783af2d7 /src/mainboard/intel | |
| parent | 340fa9396b4b73fd894a15fe48882c98d74292ce (diff) | |
Restructure i3100 Super I/O driver to match the rest of the codebase.
- i3100_early_serial.c:
- Split out enter/exit functions as the other Super I/Os do.
- Make i3100_enable_serial() take a device_t as usual, and convert
it to use the standard pnp_* function instead of open-coding
the same functionality by hand.
- Factor out i3100_configure_uart_clk() from i3100_enable_serial(),
we do the same in various other Super I/Os, e.g. ITE ones.
- Add some #defines for register / bit values and some comments.
- Only functional change: Don't set bit 1 of SIW_CONFIGURATION, it's
marked as "READ ONLY, WRITES IGNORED" in the datasheet.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/eagleheights/romstage.c | 6 | ||||
| -rw-r--r-- | src/mainboard/intel/mtarvon/romstage.c | 7 | ||||
| -rw-r--r-- | src/mainboard/intel/truxton/romstage.c | 7 |
3 files changed, 16 insertions, 4 deletions
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 8ffe22c168..8e1d212363 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -91,6 +91,8 @@ static inline int spd_read_byte(u16 device, u8 address) #include "northbridge/intel/i3100/reset_test.c" #include "debug.c" +#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1) + static void early_config(void) { u32 gcs, rpc, fd; @@ -157,7 +159,9 @@ void main(unsigned long bist) /* Setup the console */ i3100_enable_superio(); - i3100_enable_serial(0x4E, I3100_SP1, CONFIG_TTYS0_BASE); + i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26); + uart_init(); console_init(); diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index 89fb5439ef..f36e4a4e68 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -40,6 +40,8 @@ #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) +#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1) + static inline int spd_read_byte(u16 device, u8 address) { return smbus_read_byte(device, address); @@ -75,9 +77,12 @@ void main(unsigned long bist) } #endif } + /* Set up the console */ i3100_enable_superio(); - i3100_enable_serial(0x4e, I3100_SP1, CONFIG_TTYS0_BASE); + i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26); + uart_init(); console_init(); diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index 3ef60b893e..4f85095d9f 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -15,7 +15,6 @@ * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * */ #include <stdint.h> @@ -54,6 +53,8 @@ static inline int spd_read_byte(u16 device, u8 address) /* #define TRUXTON_DEBUG */ +#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1) + static void main(unsigned long bist) { msr_t msr; @@ -76,7 +77,9 @@ static void main(unsigned long bist) /* Set up the console */ i3100_enable_superio(); - i3100_enable_serial(I3100_SUPERIO_CONFIG_PORT, I3100_SP1, CONFIG_TTYS0_BASE); + i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26); + uart_init(); console_init(); |