diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2018-06-04 10:05:07 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2018-06-05 15:51:27 +0000 |
| commit | ce23d4c6f179358bf84cbdfa678d0435ae3b4cbe (patch) | |
| tree | 6c04f673fc39d2722fd9e60192cff1e6ae0f4dd6 /src/mainboard/intel | |
| parent | a0ad6e7873188ddb3a096d49548a7464450f914b (diff) | |
soc/intel/skylake: Add option to skip coreboot MP init
This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.
Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init
Default coreboot does MP initialization.
Change-Id: I8de24e662963f4600209ad1b110dc950ecfb3a27
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26818
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
5 files changed, 2 insertions, 9 deletions
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb index a8e835e95c..8751255076 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/devicetree.cb @@ -131,8 +131,6 @@ chip soc/intel/skylake .voltage_limit = 0x5F0 \ }" - register "FspSkipMpInit" = "1" - # Enable Root ports. # PCIE Port 1 x4 -> SLOT1 register "PcieRpEnable[0]" = "1" diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb index 5c41f22d8a..f07d38199f 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/devicetree.cb @@ -132,8 +132,6 @@ chip soc/intel/skylake .voltage_limit = 0x0 \ }" - register "FspSkipMpInit" = "1" - # Enable Root ports. register "PcieRpEnable[2]" = "1" register "PcieRpEnable[3]" = "1" diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb index 2a2d761af1..0057a288a4 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/devicetree.cb @@ -128,8 +128,6 @@ chip soc/intel/skylake .voltage_limit = 0x0 \ }" - register "FspSkipMpInit" = "1" - # Enable Root port. register "PcieRpEnable[3]" = "1" register "PcieRpEnable[4]" = "1" diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index aec57b1ffa..44aa325bff 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -141,8 +141,6 @@ chip soc/intel/skylake .voltage_limit = 0x5F0 \ }" - register "FspSkipMpInit" = "1" - # Enable Root port 1 and 5. register "PcieRpEnable[0]" = "1" register "PcieRpEnable[4]" = "1" diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 6da73dc412..43d14ede49 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -142,7 +142,8 @@ chip soc/intel/skylake .voltage_limit = 0x5F0 \ }" - register "FspSkipMpInit" = "0" + # Skip coreboot MP Init + register "use_fsp_mp_init" = "1" # Enable x1 slot register "PcieRpEnable[7]" = "1" |