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authorMichael Niewöhner <foss@mniewoehner.de>2021-04-10 22:51:15 +0200
committerMichael Niewöhner <foss@mniewoehner.de>2021-04-12 16:52:19 +0000
commitc5f1dc96bf0b18245d7986463ae56958c44d24f2 (patch)
treeed6b20f2b323d3ff835812aa98bf9450b177c4ec /src/mainboard/intel
parentc1ec940eba11d279912b24377a7cf8ab4b264aaa (diff)
mb/*: drop LPC generic range for port 80
Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have to be set up as generic range. Drop the entries from the devicetrees. Change-Id: I8a54d3c35a321a2d57bd846662f7339eff53e5a8 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/adlrvp/devicetree.cb1
-rw-r--r--src/mainboard/intel/adlrvp/devicetree_m.cb1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 57d78de9ce..5ca8468118 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -41,7 +41,6 @@ chip soc/intel/alderlake
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
- register "gen4_dec" = "0x000c0081"
# This disabled autonomous GPIO power management, otherwise
# old cr50 FW only supports short pulses; need to clarify
diff --git a/src/mainboard/intel/adlrvp/devicetree_m.cb b/src/mainboard/intel/adlrvp/devicetree_m.cb
index 7c691638c7..c6c2537978 100644
--- a/src/mainboard/intel/adlrvp/devicetree_m.cb
+++ b/src/mainboard/intel/adlrvp/devicetree_m.cb
@@ -34,7 +34,6 @@ chip soc/intel/alderlake
register "gen2_dec" = "0x000c0201"
# EC memory map range is 0x900-0x9ff
register "gen3_dec" = "0x00fc0901"
- register "gen4_dec" = "0x000c0081"
register "PrmrrSize" = "0"