mb/*: Remove old USB configurations from SNB/bd82x6x boards

Remove USB configurations and data structures from northbridge
devicetree (SNB+MRC boards) and bootblock/romstage C code
(native-only SNB boards). All USB configurations are drawn from
southbridge devicetree going forward.

Change-Id: Ie1cd21077136998a6e90050c95263f2efed68a67
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81882
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

6 files changed, 0 insertions, 94 deletions

diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb
index 8b10b6b36c..954f572b31 100644
--- a/src/mainboard/intel/dcp847ske/devicetree.cb
+++ b/src/mainboard/intel/dcp847ske/devicetree.cb
@@ -15,22 +15,6 @@ chip northbridge/intel/sandybridge
 	register "max_mem_clock_mhz" = "666"
 	register "spd_addresses" = "{0x50, 0, 0x51, 0}"
 
-	register "usb_port_config" = "{
-		{1, 0, 0x0040},
-		{1, 0, 0x0040},
-		{1, 1, 0x0040},
-		{1, 1, 0x0040},
-		{1, 2, 0x0040},
-		{1, 2, 0x0040},
-		{1, 3, 0x0040},
-		{0, 3, 0x0040},
-		{0, 4, 0x0040},
-		{0, 4, 0x0040},
-		{0, 5, 0x0040},
-		{0, 5, 0x0040},
-		{0, 6, 0x0040},
-		{0, 6, 0x0040},	}"
-
 	device domain 0 on
 		device ref host_bridge on  end	# Host bridge
 		device ref peg10 off end	# PCIe Bridge for discrete graphics
diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c
index e0f27bab51..a137e35d42 100644
--- a/src/mainboard/intel/dcp847ske/early_southbridge.c
+++ b/src/mainboard/intel/dcp847ske/early_southbridge.c
@@ -124,8 +124,3 @@ void bootblock_mainboard_early_init(void)
 	superio_init();
 	hwm_init();
 }
-
-const struct southbridge_usb_port mainboard_usb_ports[] = {
-#define USB_CONFIG(enabled, current, ocpin) { enabled, current, ocpin }
-#include "usb.h"
-};
diff --git a/src/mainboard/intel/dcp847ske/usb.h b/src/mainboard/intel/dcp847ske/usb.h
deleted file mode 100644
index 24693098a6..0000000000
--- a/src/mainboard/intel/dcp847ske/usb.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef DCP847SKE_USB_H
-#define DCP847SKE_USB_H
-
-USB_CONFIG(1, 1, 0), /* back, towards HDMI plugs */
-USB_CONFIG(1, 1, 0), /* back, towards power plug */
-USB_CONFIG(1, 1, 1), /* half-width miniPCIe */
-USB_CONFIG(1, 1, 1), /* full-width miniPCIe */
-USB_CONFIG(1, 1, 2), /* front-panel header */
-USB_CONFIG(1, 1, 2), /* front-panel header */
-USB_CONFIG(1, 1, 3), /* front connector */
-USB_CONFIG(0, 1, 3), /* not available */
-USB_CONFIG(0, 1, 4), /* not available */
-USB_CONFIG(0, 1, 4), /* not available */
-USB_CONFIG(0, 1, 5), /* not available */
-USB_CONFIG(0, 1, 5), /* not available */
-USB_CONFIG(0, 1, 6), /* not available */
-USB_CONFIG(0, 1, 6), /* not available */
-
-#endif
diff --git a/src/mainboard/intel/dq67sw/early_init.c b/src/mainboard/intel/dq67sw/early_init.c
index 14317a69e0..f7515a540c 100644
--- a/src/mainboard/intel/dq67sw/early_init.c
+++ b/src/mainboard/intel/dq67sw/early_init.c
@@ -1,29 +1,11 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <bootblock_common.h>
-#include <southbridge/intel/bd82x6x/pch.h>
 #include <superio/winbond/w83667hg-a/w83667hg-a.h>
 #include <superio/winbond/common/winbond.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
 
-const struct southbridge_usb_port mainboard_usb_ports[] = {
-	{ 1, 1, 0 },
-	{ 1, 1, 0 },
-	{ 1, 1, 1 },
-	{ 1, 1, 1 },
-	{ 1, 0, 2 },
-	{ 1, 0, 2 },
-	{ 1, 0, 3 },
-	{ 1, 0, 3 },
-	{ 1, 1, 4 },
-	{ 1, 1, 4 },
-	{ 0, 0, 5 },
-	{ 0, 0, 5 },
-	{ 1, 0, 6 },
-	{ 1, 0, 6 },
-};
-
 void bootblock_mainboard_early_init(void)
 {
 	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb
index 75e6daa1a3..e547ff111f 100644
--- a/src/mainboard/intel/emeraldlake2/devicetree.cb
+++ b/src/mainboard/intel/emeraldlake2/devicetree.cb
@@ -14,22 +14,6 @@ chip northbridge/intel/sandybridge
 	register "max_mem_clock_mhz" = "800"
 	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
 
-	register "usb_port_config" = "{
-		{ 1, 0, 0x0040 },
-		{ 1, 1, 0x0040 },
-		{ 1, 0, 0x0040 },
-		{ 1, 0, 0x0040 },
-		{ 1, 2, 0x0040 },
-		{ 0, 0, 0x0000 },
-		{ 0, 0, 0x0000 },
-		{ 0, 0, 0x0000 },
-		{ 1, 4, 0x0040 },
-		{ 1, 4, 0x0040 },
-		{ 1, 4, 0x0040 },
-		{ 0, 4, 0x0000 },
-		{ 1, 6, 0x0040 },
-		{ 1, 5, 0x0040 }, }"
-
 	chip cpu/intel/model_206ax
 		device cpu_cluster 0 on end
 
diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c
index 1974713520..329f13d2c1 100644
--- a/src/mainboard/intel/emeraldlake2/early_init.c
+++ b/src/mainboard/intel/emeraldlake2/early_init.c
@@ -47,21 +47,3 @@ void bootblock_mainboard_early_init(void)
 void mainboard_fill_pei_data(struct pei_data *pei_data)
 {
 }
-
-const struct southbridge_usb_port mainboard_usb_ports[] = {
-	/* enabled power  USB oc pin  */
-	{ 1, 0, 0 }, /* P0: Front port  (OC0) */
-	{ 1, 0, 1 }, /* P1: Back port   (OC1) */
-	{ 1, 0, -1 }, /* P2: MINIPCIE1   (no OC) */
-	{ 1, 0, -1 }, /* P3: MMC         (no OC) */
-	{ 1, 0, 2 }, /* P4: Front port  (OC2) */
-	{ 0, 0, -1 }, /* P5: Empty */
-	{ 0, 0, -1 }, /* P6: Empty */
-	{ 0, 0, -1 }, /* P7: Empty */
-	{ 1, 0, 4 }, /* P8: Back port   (OC4) */
-	{ 1, 0, -1 }, /* P9: MINIPCIE3   (no OC) */
-	{ 1, 0, -1 }, /* P10: BLUETOOTH  (no OC) */
-	{ 0, 0, -1 }, /* P11: Empty */
-	{ 1, 0, 6 }, /* P12: Back port  (OC6) */
-	{ 1, 0, 5 }, /* P13: Back port  (OC5) */
-};