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authorMario Scheithauer <mario.scheithauer@siemens.com>2023-05-31 14:36:22 +0200
committerFelix Singer <service+coreboot-gerrit@felixsinger.de>2023-06-02 17:58:46 +0000
commit7e5b28feb6a0b14c4303b9610bee3277dd8077fe (patch)
tree9045f9d524e05113c8b58b2264651651e40bf2b0 /src/mainboard/intel
parent923215184d3720d836c2be75a95c629af6dac7c9 (diff)
soc/intel/apollolake: Switch to snake case for SataPortsEnable
For a unification of the naming convension, change from pascal case to snake case style for parameter 'SataPortsEnable'. Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75553 Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/apollolake_rvp/devicetree.cb4
-rw-r--r--src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb4
-rw-r--r--src/mainboard/intel/leafhill/devicetree.cb4
-rw-r--r--src/mainboard/intel/minnow3/devicetree.cb4
4 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb
index a983807f4f..bf20913c8a 100644
--- a/src/mainboard/intel/apollolake_rvp/devicetree.cb
+++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb
@@ -21,8 +21,8 @@ chip soc/intel/apollolake
device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on # - SATA
- register "SataPortsEnable[0]" = "1"
- register "SataPortsEnable[1]" = "1"
+ register "sata_ports_enable[0]" = "1"
+ register "sata_ports_enable[1]" = "1"
end
device pci 13.0 on end # - PCIe-A 0
device pci 13.2 on end # - Onboard Lan
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
index 551fc60d52..294d4680e2 100644
--- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
+++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
@@ -121,8 +121,8 @@ chip soc/intel/apollolake
device pci 0f.2 on end # - Heci3
device pci 11.0 off end # - ISH
device pci 12.0 on # - SATA
- register "SataPortsEnable[0]" = "1"
- register "SataPortsEnable[1]" = "1"
+ register "sata_ports_enable[0]" = "1"
+ register "sata_ports_enable[1]" = "1"
end
device pci 13.0 off end # - PCIe-A 0 Slot 1
device pci 13.1 off end # - PCIe-A 1
diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb
index 0a152b6a4a..c1bfb97e1f 100644
--- a/src/mainboard/intel/leafhill/devicetree.cb
+++ b/src/mainboard/intel/leafhill/devicetree.cb
@@ -21,8 +21,8 @@ chip soc/intel/apollolake
device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on # - SATA
- register "SataPortsEnable[0]" = "1"
- register "SataPortsEnable[1]" = "1"
+ register "sata_ports_enable[0]" = "1"
+ register "sata_ports_enable[1]" = "1"
end
device pci 13.0 on end # - PCIe-A 0
device pci 13.2 on end # - Onboard Lan
diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb
index 0a152b6a4a..c1bfb97e1f 100644
--- a/src/mainboard/intel/minnow3/devicetree.cb
+++ b/src/mainboard/intel/minnow3/devicetree.cb
@@ -21,8 +21,8 @@ chip soc/intel/apollolake
device pci 0f.0 on end # - CSE
device pci 11.0 on end # - ISH
device pci 12.0 on # - SATA
- register "SataPortsEnable[0]" = "1"
- register "SataPortsEnable[1]" = "1"
+ register "sata_ports_enable[0]" = "1"
+ register "sata_ports_enable[1]" = "1"
end
device pci 13.0 on end # - PCIe-A 0
device pci 13.2 on end # - Onboard Lan