mainboard/*/romstage.c: Sanitize system header inclusions

Fix system include paths to be consistent. Chipset support is
part of the Coreboot 'system' and hence 'non-local' (i.e., in
the same directory or context). One possible product of this, is
to perhaps allow future work to do pre-compiled headers (PCH) on
the buildbot for faster build times. However, this currently just
makes mainboard's consistent.

Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8085
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>

8 files changed, 26 insertions, 26 deletions

diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c
index e02ae7aad1..7aea6b6eae 100644
--- a/src/mainboard/intel/baskingridge/romstage.c
+++ b/src/mainboard/intel/baskingridge/romstage.c
@@ -21,10 +21,10 @@
 #include <stdint.h>
 #include <stddef.h>
 #include <console/console.h>
-#include "cpu/intel/haswell/haswell.h"
-#include "northbridge/intel/haswell/haswell.h"
-#include "northbridge/intel/haswell/raminit.h"
-#include "southbridge/intel/lynxpoint/pch.h"
+#include <cpu/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/raminit.h>
+#include <southbridge/intel/lynxpoint/pch.h>
 #include "gpio.h"
 
 const struct rcba_config_instruction rcba_config[] = {
diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index a660df2a25..72832ea4cb 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -35,11 +35,11 @@
 #include <reset.h>
 #include <superio/smsc/sio1007/chip.h>
 #include <fsp_util.h>
-#include "northbridge/intel/fsp_sandybridge/northbridge.h"
-#include "northbridge/intel/fsp_sandybridge/raminit.h"
-#include "southbridge/intel/fsp_bd82x6x/pch.h"
-#include "southbridge/intel/fsp_bd82x6x/gpio.h"
-#include "southbridge/intel/fsp_bd82x6x/me.h"
+#include <northbridge/intel/fsp_sandybridge/northbridge.h>
+#include <northbridge/intel/fsp_sandybridge/raminit.h>
+#include <southbridge/intel/fsp_bd82x6x/pch.h>
+#include <southbridge/intel/fsp_bd82x6x/gpio.h>
+#include <southbridge/intel/fsp_bd82x6x/me.h>
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include "gpio.h"
diff --git a/src/mainboard/intel/d810e2cb/romstage.c b/src/mainboard/intel/d810e2cb/romstage.c
index a6958eeaae..e7b78f8052 100644
--- a/src/mainboard/intel/d810e2cb/romstage.c
+++ b/src/mainboard/intel/d810e2cb/romstage.c
@@ -24,10 +24,10 @@
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <console/console.h>
-#include "southbridge/intel/i82801bx/i82801bx.h"
-#include "northbridge/intel/i82810/raminit.h"
+#include <southbridge/intel/i82801bx/i82801bx.h>
+#include <northbridge/intel/i82810/raminit.h>
 #include "drivers/pc80/udelay_io.c"
-#include "cpu/x86/bist.h"
+#include <cpu/x86/bist.h>
 #include <superio/smsc/smscsuperio/smscsuperio.h>
 #include "gpio.c"
 #include <lib.h>
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 4194a80aaa..c8b53ed188 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -32,9 +32,9 @@
 #include <pc80/mc146818rtc.h>
 #include <console/console.h>
 #include <cpu/x86/bist.h>
-#include "northbridge/intel/i945/i945.h"
-#include "northbridge/intel/i945/raminit.h"
-#include "southbridge/intel/i82801gx/i82801gx.h"
+#include <northbridge/intel/i945/i945.h>
+#include <northbridge/intel/i945/raminit.h>
+#include <southbridge/intel/i82801gx/i82801gx.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, LPC47M15X_SP1)
 #define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME)
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index b41e0c5cae..b0efb7d0f2 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -35,8 +35,8 @@
 #include "southbridge/intel/i3100/reset.c"
 #include <superio/intel/i3100/i3100.h>
 #include <superio/smsc/smscsuperio/smscsuperio.h>
-#include "northbridge/intel/i3100/i3100.h"
-#include "southbridge/intel/i3100/i3100.h"
+#include <northbridge/intel/i3100/i3100.h>
+#include <southbridge/intel/i3100/i3100.h>
 #include "lib/debug.c" // XXX
 
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
@@ -67,7 +67,7 @@ static inline int spd_read_byte(u16 device, u8 address)
 	return smbus_read_byte(device, address);
 }
 
-#include "northbridge/intel/i3100/raminit.h"
+#include <northbridge/intel/i3100/raminit.h>
 #include "northbridge/intel/i3100/memory_initialized.c"
 #include "northbridge/intel/i3100/raminit.c"
 #include "lib/generic_sdram.c"
diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c
index ffb44a0423..adcf175d04 100644
--- a/src/mainboard/intel/emeraldlake2/romstage.c
+++ b/src/mainboard/intel/emeraldlake2/romstage.c
@@ -31,10 +31,10 @@
 #include <cbmem.h>
 #include <console/console.h>
 #include <superio/smsc/sio1007/chip.h>
-#include "northbridge/intel/sandybridge/sandybridge.h"
-#include "northbridge/intel/sandybridge/raminit.h"
-#include "southbridge/intel/bd82x6x/pch.h"
-#include "southbridge/intel/bd82x6x/gpio.h"
+#include <northbridge/intel/sandybridge/sandybridge.h>
+#include <northbridge/intel/sandybridge/raminit.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <southbridge/intel/bd82x6x/gpio.h>
 #include <arch/cpu.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/msr.h>
diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c
index 959beab260..61f9a2c3cb 100644
--- a/src/mainboard/intel/mtarvon/romstage.c
+++ b/src/mainboard/intel/mtarvon/romstage.c
@@ -28,10 +28,10 @@
 #include <console/console.h>
 #include "southbridge/intel/i3100/early_smbus.c"
 #include "southbridge/intel/i3100/early_lpc.c"
-#include "northbridge/intel/i3100/raminit.h"
+#include <northbridge/intel/i3100/raminit.h>
 #include <superio/intel/i3100/i3100.h>
 #include "northbridge/intel/i3100/memory_initialized.c"
-#include "cpu/x86/bist.h"
+#include <cpu/x86/bist.h>
 #include <spd.h>
 
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0)
diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c
index 4c15f672a0..5145a50ced 100644
--- a/src/mainboard/intel/truxton/romstage.c
+++ b/src/mainboard/intel/truxton/romstage.c
@@ -29,11 +29,11 @@
 #include <console/console.h>
 #include "southbridge/intel/i3100/early_smbus.c"
 #include "southbridge/intel/i3100/early_lpc.c"
-#include "northbridge/intel/i3100/raminit_ep80579.h"
+#include <northbridge/intel/i3100/raminit_ep80579.h>
 #include <superio/intel/i3100/i3100.h>
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "lib/debug.c" // XXX
-#include "cpu/x86/bist.h"
+#include <cpu/x86/bist.h>
 #include <spd.h>
 
 #define DEVPRES_CONFIG  (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0)