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authorCliff Huang <cliff.huang@intel.com>2021-08-19 14:32:50 -0700
committerFelix Held <felix-coreboot@felixheld.de>2021-08-30 12:20:28 +0000
commit73ed5991bc42caf306fd6f2b13696853b7069e02 (patch)
treea994da5ad3ceb7e17064f5e7b50b9c3cf54f26a8 /src/mainboard/intel
parentced18c6777d622775170286c4a08414c40d783f2 (diff)
mb/intel/adlrvp_m: Fix to Enable PCIe x1 Slot
This fix will enable PCIe x1 slot for ADL-M LP4 and LP5 RVPs. The BDF for this PCIe slot is pci is: 0000:00:1d.0 TEST = show device command: $ lspci -s 00:19.0 expect this: 00:19.0 Serial bus controller [0c80]: Intel Corporation Device 51c5 Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Ia988fa0b5d8fefe68503b39843aab06c4229b36f Reviewed-on: https://review.coreboot.org/c/coreboot/+/57053 Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/adlrvp/gpio_m.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/gpio_m.c b/src/mainboard/intel/adlrvp/gpio_m.c
index f6230cff3e..12048dcee0 100644
--- a/src/mainboard/intel/adlrvp/gpio_m.c
+++ b/src/mainboard/intel/adlrvp/gpio_m.c
@@ -26,6 +26,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
/* D15 : WWAN_DISABLE_N */
PAD_CFG_GPO(GPP_D15, 1, PLTRST),
+ /* D17 : PCIE SLOT1 WAKE N */
+ PAD_CFG_GPI_IRQ_WAKE(GPP_D17, NONE, DEEP, LEVEL, INVERT),
/* D18 : WWAN WAKE N*/
PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT),
/* H23 : CLKREQ5_WWAN_N */
@@ -45,6 +47,8 @@ static const struct pad_config gpio_table[] = {
PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
/* F6 : GPPC_F6_CNV_PA_BLANKING */
PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
+ /* F10 : GPPC_F10 X1_Slot_RESET */
+ PAD_CFG_GPO(GPP_F10, 1, PLTRST),
/* H8 : CNV_MFUART2_RXD */
PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
/* H9 : CNV_MFUART2_TXD */