skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope

Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Marvin Evers <marvin.n.evers@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>

6 files changed, 156 insertions, 146 deletions

diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
index b580e76241..f2e569ddfd 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb
@@ -46,35 +46,6 @@ chip soc/intel/skylake
 	# USB related
 	register "SsicPortEnable" = "1"
 
-	register "usb2_ports" = "{
-		[0] = USB2_PORT_MID(OC_SKIP),	/* OTG */
-		[1] = USB2_PORT_MID(OC3),	/* Touch Pad */
-		[2] = USB2_PORT_MID(OC_SKIP),	/* M.2 BT */
-		[3] = USB2_PORT_MID(OC_SKIP),	/* Touch Panel */
-		[4] = USB2_PORT_MID(OC_SKIP),	/* M.2 WWAN */
-		[5] = USB2_PORT_MID(OC0),	/* Front Panel */
-		[6] = USB2_PORT_MID(OC0),	/* Front Panel */
-		[7] = USB2_PORT_MID(OC2),	/* Stacked conn (lan + usb) */
-		[8] = USB2_PORT_MID(OC2),	/* Stacked conn (lan + usb) */
-		[9] = USB2_PORT_MID(OC1),	/* LAN MAGJACK */
-		[10] = USB2_PORT_MID(OC1),	/* LAN MAGJACK */
-		[11] = USB2_PORT_MID(OC_SKIP),	/* Finger print sensor */
-		[12] = USB2_PORT_MID(OC4),	/* USB 2 stack conn */
-		[13] = USB2_PORT_MID(OC4),	/* USB 2 stack conn */
-	}"
-
-	register "usb3_ports" = "{
-		[0] = USB3_PORT_DEFAULT(OC5),		/* OTG */
-		[1] = USB3_PORT_DEFAULT(OC_SKIP),	/* M.2 WWAN */
-		[2] = USB3_PORT_DEFAULT(OC3),		/* Flex */
-		[3] = USB3_PORT_DEFAULT(OC_SKIP),	/* IVCAM */
-		[4] = USB3_PORT_DEFAULT(OC1),		/* LAN MAGJACK */
-		[5] = USB3_PORT_DEFAULT(OC0),		/* Front Panel */
-		[6] = USB3_PORT_DEFAULT(OC0),		/* Front Panel */
-		[7] = USB3_PORT_DEFAULT(OC2),		/* Stack Conn */
-		[8] = USB3_PORT_DEFAULT(OC2),		/* Stack Conn */
-		[9] = USB3_PORT_DEFAULT(OC1),		/* LAN MAGJACK */
-	}"
 
 	register "SataSalpSupport" = "1"
 	register "SataPortsEnable" = "{
@@ -107,6 +78,37 @@ chip soc/intel/skylake
 	}"
 
 	device domain 0 on
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC_SKIP),	/* OTG */
+				[1] = USB2_PORT_MID(OC3),	/* Touch Pad */
+				[2] = USB2_PORT_MID(OC_SKIP),	/* M.2 BT */
+				[3] = USB2_PORT_MID(OC_SKIP),	/* Touch Panel */
+				[4] = USB2_PORT_MID(OC_SKIP),	/* M.2 WWAN */
+				[5] = USB2_PORT_MID(OC0),	/* Front Panel */
+				[6] = USB2_PORT_MID(OC0),	/* Front Panel */
+				[7] = USB2_PORT_MID(OC2),	/* Stacked conn (lan + usb) */
+				[8] = USB2_PORT_MID(OC2),	/* Stacked conn (lan + usb) */
+				[9] = USB2_PORT_MID(OC1),	/* LAN MAGJACK */
+				[10] = USB2_PORT_MID(OC1),	/* LAN MAGJACK */
+				[11] = USB2_PORT_MID(OC_SKIP),	/* Finger print sensor */
+				[12] = USB2_PORT_MID(OC4),	/* USB 2 stack conn */
+				[13] = USB2_PORT_MID(OC4),	/* USB 2 stack conn */
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC5),		/* OTG */
+				[1] = USB3_PORT_DEFAULT(OC_SKIP),	/* M.2 WWAN */
+				[2] = USB3_PORT_DEFAULT(OC3),		/* Flex */
+				[3] = USB3_PORT_DEFAULT(OC_SKIP),	/* IVCAM */
+				[4] = USB3_PORT_DEFAULT(OC1),		/* LAN MAGJACK */
+				[5] = USB3_PORT_DEFAULT(OC0),		/* Front Panel */
+				[6] = USB3_PORT_DEFAULT(OC0),		/* Front Panel */
+				[7] = USB3_PORT_DEFAULT(OC2),		/* Stack Conn */
+				[8] = USB3_PORT_DEFAULT(OC2),		/* Stack Conn */
+				[9] = USB3_PORT_DEFAULT(OC1),		/* LAN MAGJACK */
+			}"
+		end
 		device ref sa_thermal	off end
 		device ref i2c2		off end
 		device ref i2c3		off end
diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
index b7c4395bd1..81557eb8ff 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb
@@ -74,26 +74,6 @@ chip soc/intel/skylake
 	# RP10, uses CLK SRC 4
 	register "PcieRpClkSrcNumber[9]" = "4"
 
-	register "usb2_ports" = "{
-		[0] = USB2_PORT_MAX(OC0),	/* TYPE-A Port */
-		[1] = USB2_PORT_MAX(OC2),	/* TYPE-A Port */
-		[2] = USB2_PORT_MAX(OC_SKIP),	/* Bluetooth */
-		[4] = USB2_PORT_MAX(OC_SKIP),	/* Type-A Port */
-		[5] = USB2_PORT_MAX(OC2),	/* TYPE-A Port */
-		[6] = USB2_PORT_MAX(OC_SKIP),	/* TYPE-A Port */
-		[7] = USB2_PORT_MAX(OC_SKIP),	/* TYPE-A Port */
-		[8] = USB2_PORT_MAX(OC_SKIP),	/* TYPE-A Port */
-		[9] = USB2_PORT_MAX(OC1),	/* TYPE-A Port */
-		[10] = USB2_PORT_MAX(OC_SKIP),	/* TYPE-A Port */
-		[11] = USB2_PORT_MAX(OC_SKIP),	/* TYPE-A Port */
-	}"
-
-	register "usb3_ports" = "{
-		[0] = USB3_PORT_DEFAULT(OC0),		/* TYPE-A Port */
-		[1] = USB3_PORT_DEFAULT(OC_SKIP),	/* TYPE-A Port */
-		[2] = USB3_PORT_DEFAULT(OC_SKIP),	/* TYPE-A Port */
-		[3] = USB3_PORT_DEFAULT(OC1),		/* TYPE-A Port */
-	}"
 
 	register "SsicPortEnable" = "1" # Enable SSIC for WWAN
 
@@ -113,6 +93,28 @@ chip soc/intel/skylake
 	}"
 
 	device domain 0 on
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MAX(OC0),	/* TYPE-A Port */
+				[1] = USB2_PORT_MAX(OC2),	/* TYPE-A Port */
+				[2] = USB2_PORT_MAX(OC_SKIP),	/* Bluetooth */
+				[4] = USB2_PORT_MAX(OC_SKIP),	/* Type-A Port */
+				[5] = USB2_PORT_MAX(OC2),	/* TYPE-A Port */
+				[6] = USB2_PORT_MAX(OC_SKIP),	/* TYPE-A Port */
+				[7] = USB2_PORT_MAX(OC_SKIP),	/* TYPE-A Port */
+				[8] = USB2_PORT_MAX(OC_SKIP),	/* TYPE-A Port */
+				[9] = USB2_PORT_MAX(OC1),	/* TYPE-A Port */
+				[10] = USB2_PORT_MAX(OC_SKIP),	/* TYPE-A Port */
+				[11] = USB2_PORT_MAX(OC_SKIP),	/* TYPE-A Port */
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),		/* TYPE-A Port */
+				[1] = USB3_PORT_DEFAULT(OC_SKIP),	/* TYPE-A Port */
+				[2] = USB3_PORT_DEFAULT(OC_SKIP),	/* TYPE-A Port */
+				[3] = USB3_PORT_DEFAULT(OC1),		/* TYPE-A Port */
+			}"
+		end
 		device ref imgu		on  end
 		device ref cio		on  end
 		device ref pcie_rp1	on  end # x4 SLOT1
diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
index ce4bf4b81b..9e8c8140ac 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb
@@ -113,28 +113,6 @@ chip soc/intel/skylake
 	# RP 9 uses CLK SRC 1#
 	register "PcieRpClkSrcNumber[8]" = "1"
 
-	register "usb2_ports" = "{
-		[0] = USB2_PORT_MAX(OC0),	/* TYPE-A Port */
-		[1] = USB2_PORT_MAX(OC2),	/* TYPE-A Port */
-		[2] = USB2_PORT_MAX(OC_SKIP),	/* Bluetooth */
-		[4] = USB2_PORT_MAX(OC1),	/* Type-A Port */
-		[5] = USB2_PORT_MAX(OC_SKIP),	/* TYPE-A Port */
-		[6] = USB2_PORT_MAX(OC2),	/* TYPE-A Port */
-		[7] = USB2_PORT_MAX(OC2),	/* TYPE-A Port */
-		[8] = USB2_PORT_MAX(OC_SKIP),	/* TYPE-A Port */
-		[9] = USB2_PORT_MAX(OC_SKIP),	/* TYPE-A Port */
-		[10] = USB2_PORT_MAX(OC_SKIP),	/* TYPE-A Port */
-		[11] = USB2_PORT_MAX(OC_SKIP),	/* TYPE-A Port */
-	}"
-
-	register "usb3_ports" = "{
-		[0] = USB3_PORT_DEFAULT(OC0),		/* TYPE-A Port */
-		[1] = USB3_PORT_DEFAULT(OC_SKIP),	/* TYPE-A Port */
-		[2] = USB3_PORT_DEFAULT(OC_SKIP),	/* TYPE-A Port */
-		[3] = USB3_PORT_DEFAULT(OC1),		/* TYPE-A Port */
-		[4] = USB3_PORT_DEFAULT(OC2),		/* TYPE-A Port */
-		[5] = USB3_PORT_DEFAULT(OC_SKIP),	/* TYPE-A Port */
-	}"
 
 	register "SerialIoDevMode" = "{
 		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
@@ -154,6 +132,30 @@ chip soc/intel/skylake
 	register "sdcard_cd_gpio" = "GPP_G5"
 
 	device domain 0 on
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MAX(OC0),	/* TYPE-A Port */
+				[1] = USB2_PORT_MAX(OC2),	/* TYPE-A Port */
+				[2] = USB2_PORT_MAX(OC_SKIP),	/* Bluetooth */
+				[4] = USB2_PORT_MAX(OC1),	/* Type-A Port */
+				[5] = USB2_PORT_MAX(OC_SKIP),	/* TYPE-A Port */
+				[6] = USB2_PORT_MAX(OC2),	/* TYPE-A Port */
+				[7] = USB2_PORT_MAX(OC2),	/* TYPE-A Port */
+				[8] = USB2_PORT_MAX(OC_SKIP),	/* TYPE-A Port */
+				[9] = USB2_PORT_MAX(OC_SKIP),	/* TYPE-A Port */
+				[10] = USB2_PORT_MAX(OC_SKIP),	/* TYPE-A Port */
+				[11] = USB2_PORT_MAX(OC_SKIP),	/* TYPE-A Port */
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),		/* TYPE-A Port */
+				[1] = USB3_PORT_DEFAULT(OC_SKIP),	/* TYPE-A Port */
+				[2] = USB3_PORT_DEFAULT(OC_SKIP),	/* TYPE-A Port */
+				[3] = USB3_PORT_DEFAULT(OC1),		/* TYPE-A Port */
+				[4] = USB3_PORT_DEFAULT(OC2),		/* TYPE-A Port */
+				[5] = USB3_PORT_DEFAULT(OC_SKIP),	/* TYPE-A Port */
+			}"
+		end
 		device ref i2c2		off end
 		device ref i2c3		off end
 		device ref sata		on  end
diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
index 2291c637fd..8e70c1e971 100644
--- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
+++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb
@@ -95,35 +95,6 @@ chip soc/intel/skylake
 	register "PcieRpClkReqNumber[8]" = "6"
 	register "PcieRpClkReqNumber[16]" = "7"
 
-	register "usb2_ports" = "{
-		[0] = USB2_PORT_MAX(OC2),	/* Type-C Port */
-		[1] = USB2_PORT_MAX(OC5),	/* Front panel */
-		[2] = USB2_PORT_MAX(OC4),	/* Back panel */
-		[3] = USB2_PORT_MAX(OC4),	/* Back panel */
-		[4] = USB2_PORT_MAX(OC1),	/* Back panel-1 */
-		[5] = USB2_PORT_MAX(OC1),	/* Back panel */
-		[6] = USB2_PORT_MAX(OC_SKIP),	/* Back panel */
-		[7] = USB2_PORT_MAX(OC_SKIP),	/* Front panel */
-		[8] = USB2_PORT_MAX(OC_SKIP),	/* M.2 BT */
-		[9] = USB2_PORT_MAX(OC2),	/* Front panel */
-		[10] = USB2_PORT_MAX(OC_SKIP),	/* Back panel */
-		[11] = USB2_PORT_MAX(OC_SKIP),	/* Back panel-1 */
-		[12] = USB2_PORT_MAX(OC3),	/* Back panel */
-		[13] = USB2_PORT_MAX(OC_SKIP),	/* Back panel */
-	}"
-
-	register "usb3_ports" = "{
-		[0] = USB3_PORT_DEFAULT(OC_SKIP),	/* Type-C Port */
-		[1] = USB3_PORT_DEFAULT(OC1),		/* Back panel */
-		[2] = USB3_PORT_DEFAULT(OC1),		/* Back panel */
-		[3] = USB3_PORT_DEFAULT(OC0),		/* Back panel-2 */
-		[4] = USB3_PORT_DEFAULT(OC0),		/* Front Panel */
-		[5] = USB3_PORT_DEFAULT(OC_SKIP),	/* Front Panel */
-		[6] = USB3_PORT_DEFAULT(OC2),		/* Front Panel */
-		[7] = USB3_PORT_DEFAULT(OC2),		/* Front Panel */
-		[8] = USB3_PORT_DEFAULT(OC3),		/* Back panel */
-		[9] = USB3_PORT_DEFAULT(OC_SKIP),	/* LAN */
-	}"
 
 	register "SsicPortEnable" = "1" # Enable SSIC for WWAN
 
@@ -160,6 +131,37 @@ chip soc/intel/skylake
 	}"
 
 	device domain 0 on
+		device ref south_xhci on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MAX(OC2),	/* Type-C Port */
+				[1] = USB2_PORT_MAX(OC5),	/* Front panel */
+				[2] = USB2_PORT_MAX(OC4),	/* Back panel */
+				[3] = USB2_PORT_MAX(OC4),	/* Back panel */
+				[4] = USB2_PORT_MAX(OC1),	/* Back panel-1 */
+				[5] = USB2_PORT_MAX(OC1),	/* Back panel */
+				[6] = USB2_PORT_MAX(OC_SKIP),	/* Back panel */
+				[7] = USB2_PORT_MAX(OC_SKIP),	/* Front panel */
+				[8] = USB2_PORT_MAX(OC_SKIP),	/* M.2 BT */
+				[9] = USB2_PORT_MAX(OC2),	/* Front panel */
+				[10] = USB2_PORT_MAX(OC_SKIP),	/* Back panel */
+				[11] = USB2_PORT_MAX(OC_SKIP),	/* Back panel-1 */
+				[12] = USB2_PORT_MAX(OC3),	/* Back panel */
+				[13] = USB2_PORT_MAX(OC_SKIP),	/* Back panel */
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC_SKIP),	/* Type-C Port */
+				[1] = USB3_PORT_DEFAULT(OC1),		/* Back panel */
+				[2] = USB3_PORT_DEFAULT(OC1),		/* Back panel */
+				[3] = USB3_PORT_DEFAULT(OC0),		/* Back panel-2 */
+				[4] = USB3_PORT_DEFAULT(OC0),		/* Front Panel */
+				[5] = USB3_PORT_DEFAULT(OC_SKIP),	/* Front Panel */
+				[6] = USB3_PORT_DEFAULT(OC2),		/* Front Panel */
+				[7] = USB3_PORT_DEFAULT(OC2),		/* Front Panel */
+				[8] = USB3_PORT_DEFAULT(OC3),		/* Back panel */
+				[9] = USB3_PORT_DEFAULT(OC_SKIP),	/* LAN */
+			}"
+		end
 		device ref i2c2		off end
 		device ref i2c3		off end
 		device ref sata		on  end
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index d09a4d1810..45f71030c8 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -117,21 +117,6 @@ chip soc/intel/skylake
 	register "PcieRpClkReqNumber[0]" = "1"
 	register "PcieRpClkReqNumber[4]" = "2"
 
-	register "usb2_ports" = "{
-		[0] = USB2_PORT_TYPE_C(OC0),	/* Type-C Port 1 */
-		[1] = USB2_PORT_TYPE_C(OC1),	/* Type-C Port 2 */
-		[2] = USB2_PORT_MID(OC_SKIP),	/* Bluetooth */
-		[4] = USB2_PORT_MID(OC2),	/* Type-A Port (card) */
-		[6] = USB2_PORT_FLEX(OC_SKIP),	/* Camera */
-		[8] = USB2_PORT_LONG(OC3),	/* Type-A Port (board) */
-	}"
-
-	register "usb3_ports" = "{
-		[0] = USB3_PORT_DEFAULT(OC0),	/* Type-C Port 1 */
-		[1] = USB3_PORT_DEFAULT(OC1),	/* Type-C Port 2 */
-		[2] = USB3_PORT_DEFAULT(OC2),	/* Type-A Port (card) */
-		[3] = USB3_PORT_DEFAULT(OC3),	/* Type-A Port (board) */
-	}"
 
 	register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"  # I2C4 is 1.8V
 
@@ -164,7 +149,23 @@ chip soc/intel/skylake
 	device domain 0 on
 		device ref igpu		on  end
 		device ref sa_thermal	on  end
-		device ref south_xhci	on  end
+		device ref south_xhci	on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_TYPE_C(OC0),	/* Type-C Port 1 */
+				[1] = USB2_PORT_TYPE_C(OC1),	/* Type-C Port 2 */
+				[2] = USB2_PORT_MID(OC_SKIP),	/* Bluetooth */
+				[4] = USB2_PORT_MID(OC2),	/* Type-A Port (card) */
+				[6] = USB2_PORT_FLEX(OC_SKIP),	/* Camera */
+				[8] = USB2_PORT_LONG(OC3),	/* Type-A Port (board) */
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC0),	/* Type-C Port 1 */
+				[1] = USB3_PORT_DEFAULT(OC1),	/* Type-C Port 2 */
+				[2] = USB3_PORT_DEFAULT(OC2),	/* Type-A Port (card) */
+				[3] = USB3_PORT_DEFAULT(OC3),	/* Type-A Port (board) */
+			}"
+		end
 		device ref thermal	on  end
 		device ref i2c0		on
 			chip drivers/i2c/generic
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb
index d888de4a24..067cb599fb 100644
--- a/src/mainboard/intel/saddlebrook/devicetree.cb
+++ b/src/mainboard/intel/saddlebrook/devicetree.cb
@@ -125,35 +125,6 @@ chip soc/intel/skylake
 	# USB related
 	register "SsicPortEnable" = "1"
 
-	register "usb2_ports" = "{
-		[0] = USB2_PORT_MID(OC_SKIP),	/* OTG */
-		[1] = USB2_PORT_MID(OC3),	/* Touch Pad */
-		[2] = USB2_PORT_MID(OC_SKIP),	/* M.2 BT */
-		[3] = USB2_PORT_MID(OC_SKIP),	/* Touch Panel */
-		[4] = USB2_PORT_MID(OC_SKIP),	/* M.2 WWAN */
-		[5] = USB2_PORT_MID(OC0),	/* Front Panel */
-		[6] = USB2_PORT_MID(OC0),	/* Front Panel */
-		[7] = USB2_PORT_MID(OC2),	/* Stacked conn (lan + usb) */
-		[8] = USB2_PORT_MID(OC2),	/* Stacked conn (lan + usb) */
-		[9] = USB2_PORT_MID(OC1),	/* LAN MAGJACK */
-		[10] = USB2_PORT_MID(OC1),	/* LAN MAGJACK */
-		[11] = USB2_PORT_MID(OC_SKIP),	/* Finger print sensor */
-		[12] = USB2_PORT_MID(OC4),	/* USB 2 stack conn */
-		[13] = USB2_PORT_MID(OC4),	/* USB 2 stack conn */
-	}"
-
-	register "usb3_ports" = "{
-		[0] = USB3_PORT_DEFAULT(OC5),		/* OTG */
-		[1] = USB3_PORT_DEFAULT(OC_SKIP),	/* M.2 WWAN */
-		[2] = USB3_PORT_DEFAULT(OC3),		/* Flex */
-		[3] = USB3_PORT_DEFAULT(OC_SKIP),	/* IVCAM */
-		[4] = USB3_PORT_DEFAULT(OC1),		/* LAN MAGJACK */
-		[5] = USB3_PORT_DEFAULT(OC0),		/* Front Panel */
-		[6] = USB3_PORT_DEFAULT(OC0),		/* Front Panel */
-		[7] = USB3_PORT_DEFAULT(OC2),		/* Stack Conn */
-		[8] = USB3_PORT_DEFAULT(OC2),		/* Stack Conn */
-		[9] = USB3_PORT_DEFAULT(OC1),		/* LAN MAGJACK */
-	}"
 
 	register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8"  # I2C4 is 1.8V
 
@@ -197,7 +168,37 @@ chip soc/intel/skylake
 
 	device domain 0 on
 		device ref igpu		on end
-		device ref south_xhci	on end
+		device ref south_xhci	on
+			register "usb2_ports" = "{
+				[0] = USB2_PORT_MID(OC_SKIP),	/* OTG */
+				[1] = USB2_PORT_MID(OC3),	/* Touch Pad */
+				[2] = USB2_PORT_MID(OC_SKIP),	/* M.2 BT */
+				[3] = USB2_PORT_MID(OC_SKIP),	/* Touch Panel */
+				[4] = USB2_PORT_MID(OC_SKIP),	/* M.2 WWAN */
+				[5] = USB2_PORT_MID(OC0),	/* Front Panel */
+				[6] = USB2_PORT_MID(OC0),	/* Front Panel */
+				[7] = USB2_PORT_MID(OC2),	/* Stacked conn (lan + usb) */
+				[8] = USB2_PORT_MID(OC2),	/* Stacked conn (lan + usb) */
+				[9] = USB2_PORT_MID(OC1),	/* LAN MAGJACK */
+				[10] = USB2_PORT_MID(OC1),	/* LAN MAGJACK */
+				[11] = USB2_PORT_MID(OC_SKIP),	/* Finger print sensor */
+				[12] = USB2_PORT_MID(OC4),	/* USB 2 stack conn */
+				[13] = USB2_PORT_MID(OC4),	/* USB 2 stack conn */
+			}"
+
+			register "usb3_ports" = "{
+				[0] = USB3_PORT_DEFAULT(OC5),		/* OTG */
+				[1] = USB3_PORT_DEFAULT(OC_SKIP),	/* M.2 WWAN */
+				[2] = USB3_PORT_DEFAULT(OC3),		/* Flex */
+				[3] = USB3_PORT_DEFAULT(OC_SKIP),	/* IVCAM */
+				[4] = USB3_PORT_DEFAULT(OC1),		/* LAN MAGJACK */
+				[5] = USB3_PORT_DEFAULT(OC0),		/* Front Panel */
+				[6] = USB3_PORT_DEFAULT(OC0),		/* Front Panel */
+				[7] = USB3_PORT_DEFAULT(OC2),		/* Stack Conn */
+				[8] = USB3_PORT_DEFAULT(OC2),		/* Stack Conn */
+				[9] = USB3_PORT_DEFAULT(OC1),		/* LAN MAGJACK */
+			}"
+		end
 		device ref thermal	on end
 		device ref i2c0		on end
 		device ref i2c1		on end