summaryrefslogtreecommitdiff
path: root/src/mainboard/intel
diff options
context:
space:
mode:
authorLijian Zhao <lijian.zhao@intel.com>2017-08-29 17:12:51 -0700
committerMartin Roth <martinroth@google.com>2017-09-06 04:45:19 +0000
commit6c0f3c7ee1d53872851dbab636787852e3572c98 (patch)
tree0756fe96ae3b274d40d7c5acc50c1455a69c0463 /src/mainboard/intel
parent78fc3fc1057b5b0d42d3446f6e22fa03fbc1a4e4 (diff)
soc/intel/cannonlake: Add dummy ACPI DSDT table
A dummy DSDT table will be created for cannonlake. Change-Id: Ia435f2a03982313c6b0c63ac25668a3300d08793 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/cannonlake_rvp/Kconfig1
-rw-r--r--src/mainboard/intel/cannonlake_rvp/acpi_tables.c0
-rw-r--r--src/mainboard/intel/cannonlake_rvp/dsdt.asl37
3 files changed, 38 insertions, 0 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/Kconfig b/src/mainboard/intel/cannonlake_rvp/Kconfig
index 35afb07718..9d2a5f2279 100644
--- a/src/mainboard/intel/cannonlake_rvp/Kconfig
+++ b/src/mainboard/intel/cannonlake_rvp/Kconfig
@@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_16384
select SOC_INTEL_CANNONLAKE
+ select HAVE_ACPI_TABLES
select GENERIC_SPD_BIN
config MAINBOARD_DIR
diff --git a/src/mainboard/intel/cannonlake_rvp/acpi_tables.c b/src/mainboard/intel/cannonlake_rvp/acpi_tables.c
new file mode 100644
index 0000000000..e69de29bb2
--- /dev/null
+++ b/src/mainboard/intel/cannonlake_rvp/acpi_tables.c
diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl
new file mode 100644
index 0000000000..410e1aca6c
--- /dev/null
+++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2015 Google Inc.
+ * Copyright (C) 2017 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x05, // DSDT revision: ACPI v5.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // global NVS and variables
+ #include <soc/intel/cannonlake/acpi/globalnvs.asl>
+
+ Scope (\_SB) {
+ }
+
+#if IS_ENABLED(CONFIG_CHROMEOS)
+ // Chrome OS specific
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+#endif
+}