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| author | Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com> | 2019-10-30 10:14:23 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-01 11:54:12 +0000 |
| commit | 55e5cb8d4e116d70c69ca5e91f4afdbffe0d5866 (patch) | |
| tree | 073031a42979c49d3b7e2f2422459d03acb90ca3 /src/mainboard/intel | |
| parent | 242a03365df149235f052a67c173b00da40140a8 (diff) | |
mb/intel/saddlebrook: Enable Chipset_lockdown coreboot config
This patch enables lockdown configuration for saddlebrook platform
BUG=None
TEST=Boot to Linux on saddlebrook and verified MRC is restored on warm, cold,
resume boot path's.
Change-Id: Ia324c118b0c8e72b66a757dee5be43ba79abbeab
Signed-off-by: Praveen Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/saddlebrook/devicetree.cb | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 385a4be19f..7d7b58bd34 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -61,6 +61,11 @@ chip soc/intel/skylake register "serirq_mode" = "SERIRQ_CONTINUOUS" + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + # VR Settings Configuration for 4 Domains #+----------------+-----------+-----------+-------------+----------+ #| Domain/Setting | SA | IA | GT Unsliced | GT | |