diff options
| author | Subrata Banik <subratabanik@google.com> | 2024-03-16 18:11:53 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-03-17 11:55:29 +0000 |
| commit | 4866712b04a4fc6f1a72cd668de0ac91fc9a2a74 (patch) | |
| tree | 2e7021967e14597ecc55b1c804baf13cf9da0051 /src/mainboard/intel | |
| parent | aaacd5083a10e03c6530a282d3d7bb8654d0c1dc (diff) | |
soc/intel/mtl: Enable RAMTOP caching at SoC level for MTL devices
This patch enables the `SOC_INTEL_COMMON_BASECODE_RAMTOP` configuration
at the SoC level for all MTL devices. This change streamlines the
configuration process, avoiding redundant selections on individual
mainboards.
BUG=b:306677879
BRANCH=firmware-rex-15709.B
TEST=Verified boot functionality on google/ovis and google/rex.
Change-Id: I3aa3a83c190d0a0e93c267222a9dca0ac7651f9c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/mtlrvp/Kconfig | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index 440466b441..36842b577a 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -19,7 +19,6 @@ config BOARD_INTEL_MTLRVP_COMMON select HAVE_ACPI_TABLES select HAVE_SPD_IN_CBFS select MAINBOARD_HAS_CHROMEOS - select SOC_INTEL_COMMON_BASECODE_RAMTOP select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT select SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_METEORLAKE_U_H |