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authorSubrata Banik <subratabanik@google.com>2022-03-10 19:12:02 +0530
committerSubrata Banik <subratabanik@google.com>2022-03-15 10:18:28 +0000
commit4703edc943985ad1429d48866cf8c070541df713 (patch)
tree1bb5edc7b089b1217bb65105ca3ad866191960f2 /src/mainboard/intel
parent47b836af96186af3cf207b0a2bc4d99ac832680d (diff)
{mb, soc}: Move mrc_cache invalidating logic into `memory` common code
Commit hash b8b40964 ( mb, soc: Add the SPD_CACHE_ENABLE) introduced per mainboard logic to invalidate the mrc_cache. This patch moves mrc_cache invalidating logic into IA common code and cleans up the code to remove unused argument `dimms_changed` from SoC and mainboard directory. BUG=b:200243989 BRANCH=firmware-brya-14505.B TEST=Able to build and boot redrix without any visible failure/errors. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/adlrvp/romstage_fsp_params.c7
-rw-r--r--src/mainboard/intel/shadowmountain/romstage.c3
2 files changed, 3 insertions, 7 deletions
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
index 8a24529f49..e29b7d44c8 100644
--- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
@@ -48,7 +48,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
const struct mb_cfg *mem_config = variant_memory_params();
int board_id = get_board_id();
const bool half_populated = false;
- bool dimms_changed = false;
const struct mem_spd memory_down_spd_info = {
.topo = MEM_TOPO_MEMORY_DOWN,
@@ -73,8 +72,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
case ADL_P_DDR4_1:
case ADL_P_DDR4_2:
case ADL_P_DDR5_1:
- memcfg_init(memupd, mem_config, &dimm_module_spd_info, half_populated,
- &dimms_changed);
+ memcfg_init(memupd, mem_config, &dimm_module_spd_info, half_populated);
break;
case ADL_P_DDR5_2:
case ADL_P_LP4_1:
@@ -84,8 +82,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
case ADL_M_LP4:
case ADL_M_LP5:
case ADL_N_LP5:
- memcfg_init(memupd, mem_config, &memory_down_spd_info, half_populated,
- &dimms_changed);
+ memcfg_init(memupd, mem_config, &memory_down_spd_info, half_populated);
break;
default:
die("Unknown board id = 0x%x\n", board_id);
diff --git a/src/mainboard/intel/shadowmountain/romstage.c b/src/mainboard/intel/shadowmountain/romstage.c
index eb08d18eed..fcd829f644 100644
--- a/src/mainboard/intel/shadowmountain/romstage.c
+++ b/src/mainboard/intel/shadowmountain/romstage.c
@@ -11,12 +11,11 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
{
const struct mb_cfg *mem_config = variant_memory_params();
const bool half_populated = false;
- bool dimms_changed = false;
const struct mem_spd lp5_spd_info = {
.topo = MEM_TOPO_MEMORY_DOWN,
.cbfs_index = variant_memory_sku(),
};
- memcfg_init(memupd, mem_config, &lp5_spd_info, half_populated, &dimms_changed);
+ memcfg_init(memupd, mem_config, &lp5_spd_info, half_populated);
}