diff options
| author | Michael Niewöhner <foss@mniewoehner.de> | 2022-01-08 20:47:11 +0100 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-01-14 00:29:38 +0000 |
| commit | 45b6080561748fe579c8ee901811cf4043383c2f (patch) | |
| tree | b9f37ad3e3962571401fafa2578788f0feb27d5a /src/mainboard/intel | |
| parent | 9f0285b6fe46d6ec76faad0c099239c227e5caa1 (diff) | |
soc/intel/tigerlake: add devicetree option PcieRpSlotImplemented
Add the UPD PcieRpSlotImplemented as devicetree option. To keep the PI
bit set for any slots of already existing boards, add set the option
PcieRpSlotImplemented=1 where appropriate.
Change-Id: Ia6f685df3c22c74ae764693329a69817bf3cd01d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 4 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 201983cc87..d01fdd6352 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -44,6 +44,10 @@ chip soc/intel/tigerlake register "PcieRpEnable[3]" = "1" register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1" + register "PcieRpSlotImplemented[2]" = "1" + register "PcieRpSlotImplemented[3]" = "1" + register "PcieRpSlotImplemented[8]" = "1" + register "PcieRpSlotImplemented[10]" = "1" # Enable RP LTR register "PcieRpLtrEnable[2]" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index d76c0f530c..c0adcc3f50 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -45,6 +45,10 @@ chip soc/intel/tigerlake register "PcieRpEnable[3]" = "1" register "PcieRpEnable[8]" = "1" register "PcieRpEnable[10]" = "1" + register "PcieRpSlotImplemented[2]" = "1" + register "PcieRpSlotImplemented[3]" = "1" + register "PcieRpSlotImplemented[8]" = "1" + register "PcieRpSlotImplemented[10]" = "1" # Enable PR LTR register "PcieRpLtrEnable[2]" = "1" |