diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-25 13:44:34 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-26 21:45:12 +0000 |
| commit | 4276050d13cb8c555f0375d4ec44d33ab5d58402 (patch) | |
| tree | c07e6d46c94c5bb055e41b5b7dfe708423543300 /src/mainboard/intel | |
| parent | 7417bb0e5a8bddbf9a56b990119fa3af56e663ac (diff) | |
mb/*/*/devicetree.cb: Normalize disabled PIRQ values
If bit 7 of a PIRQ route is set, it is disabled. Modern OSes don't use
PIRQ routing, so we might as well zero the other bits for consistency.
Tested on Asrock B85M Pro4 with SeaBIOS 1.13.0, still boots.
Change-Id: I78980b9ea5e878a6200df0f6c18c5e7d06a7950a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43861
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/baskingridge/devicetree.cb | 8 | ||||
| -rw-r--r-- | src/mainboard/intel/wtm2/devicetree.cb | 8 |
2 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index 157f393454..8ea8e97c61 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -32,10 +32,10 @@ chip northbridge/intel/haswell device pci 02.0 on end # vga controller chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" + register "pirqa_routing" = "0x80" + register "pirqb_routing" = "0x80" + register "pirqc_routing" = "0x80" + register "pirqd_routing" = "0x80" register "pirqe_routing" = "0x80" register "pirqf_routing" = "0x80" register "pirqg_routing" = "0x80" diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index 8d36f04d54..88c033ea4d 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -9,10 +9,10 @@ chip soc/intel/broadwell # Enable DVI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" + register "pirqa_routing" = "0x80" + register "pirqb_routing" = "0x80" + register "pirqc_routing" = "0x80" + register "pirqd_routing" = "0x80" register "pirqe_routing" = "0x80" register "pirqf_routing" = "0x80" register "pirqg_routing" = "0x80" |