diff options
| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2020-01-02 16:11:27 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-17 16:03:19 +0000 |
| commit | 2f2c7ebfb4059220179cd16e2c7d0f422fbe5841 (patch) | |
| tree | b632aed51bee1b1725f2a62f88262d9f124d46e6 /src/mainboard/intel | |
| parent | 6ca5b475bf286ee8827edee64df5d14b09d936cd (diff) | |
soc/intel/tigerlake: Enable Audio on TGL
Configure UPDs to support Audio enablement.
Correct the upd name in jslrvp devicetree to avoid compilation issue.
BUG=b:147436144
BRANCH=none
TEST=Build and boot tigerlake rvp board
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Idd3927a33d303ed5a663b5b838f43ed4ebc7a0db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index fb636251da..843de142b3 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -46,7 +46,7 @@ chip soc/intel/tigerlake register "gen3_dec" = "0x00fc0901" register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHda" = "1" + register "PchHdaAudioLinkHdaEnable" = "1" # PCIe port 1 for M.2 E-key WLAN register "PcieRpEnable[1]" = "1" |