mb/*/*: Drop Intel Rangeley mainboards

Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.

Change-Id: Id38eada2d08426520261d4824990a49f8302976b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>

42 files changed, 0 insertions, 1825 deletions

diff --git a/src/mainboard/intel/littleplains/Kconfig b/src/mainboard/intel/littleplains/Kconfig
deleted file mode 100644
index b5a57b798b..0000000000
--- a/src/mainboard/intel/littleplains/Kconfig
+++ /dev/null
@@ -1,67 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-if BOARD_INTEL_LITTLEPLAINS
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select NORTHBRIDGE_INTEL_FSP_RANGELEY
-	select SOUTHBRIDGE_INTEL_FSP_RANGELEY
-	select BOARD_ROMSIZE_KB_8192
-	select HAVE_ACPI_TABLES
-	select HAVE_OPTION_TABLE
-	select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
-
-config MAINBOARD_DIR
-	string
-	default intel/littleplains
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Little Plains"
-
-config MAX_CPUS
-	int
-	default 16
-
-config CBFS_SIZE
-	hex
-	default 0x400000
-
-config ENABLE_FSP_FAST_BOOT
-	bool
-	depends on HAVE_FSP_BIN
-	default y
-
-config FSP_PACKAGE_DEFAULT
-	bool "Configure defaults for the Intel FSP package"
-	default n
-
-config UART_FOR_CONSOLE
-	int
-	default 1
-	help
-	  The Little Plains board uses COM2 (2f8) for the serial console.
-
-config PAYLOAD_CONFIGFILE
-	string
-	depends on PAYLOAD_SEABIOS
-	default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios"
-	help
-	  The Avoton/Rangeley chip does not allow devices to write into the 0xe000
-	  segment.  This means that USB/SATA devices will not work in SeaBIOS unless
-	  we put the SeaBIOS buffer area down in the 0x9000 segment.
-
-endif # BOARD_INTEL_LITTLEPLAINS
diff --git a/src/mainboard/intel/littleplains/Kconfig.name b/src/mainboard/intel/littleplains/Kconfig.name
deleted file mode 100644
index 8019eeefc8..0000000000
--- a/src/mainboard/intel/littleplains/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_INTEL_LITTLEPLAINS
-	bool "Little Plains"
diff --git a/src/mainboard/intel/littleplains/Makefile.inc b/src/mainboard/intel/littleplains/Makefile.inc
deleted file mode 100644
index c34ef4b006..0000000000
--- a/src/mainboard/intel/littleplains/Makefile.inc
+++ /dev/null
@@ -1,16 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2014 Sage Electronics Engineering, LLC.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-ramstage-y += irqroute.c
diff --git a/src/mainboard/intel/littleplains/acpi/ec.asl b/src/mainboard/intel/littleplains/acpi/ec.asl
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/intel/littleplains/acpi/ec.asl
+++ /dev/null
diff --git a/src/mainboard/intel/littleplains/acpi/mainboard.asl b/src/mainboard/intel/littleplains/acpi/mainboard.asl
deleted file mode 100644
index aecc2b6905..0000000000
--- a/src/mainboard/intel/littleplains/acpi/mainboard.asl
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-// #define ACPI_INCLUDE_PMIO 1 /* uncomment to enable PMIO block in soc.asl */
-// #define ACPI_INCLUDE_GPIO 1 /* uncomment to enable GPIO block in soc.asl */
-
-Device (PWRB)
-{
-	Name(_HID, EisaId("PNP0C0C"))
-
-	// Wake
-	Name(_PRW, Package(){0x1d, 0x05})
-}
diff --git a/src/mainboard/intel/littleplains/acpi/platform.asl b/src/mainboard/intel/littleplains/acpi/platform.asl
deleted file mode 100644
index 059cd740ff..0000000000
--- a/src/mainboard/intel/littleplains/acpi/platform.asl
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* The _WAK method is called on system wakeup */
-
-Method(_WAK,1)
-{
-	Return(Package(){0,0})
-}
diff --git a/src/mainboard/intel/littleplains/acpi/superio.asl b/src/mainboard/intel/littleplains/acpi/superio.asl
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/intel/littleplains/acpi/superio.asl
+++ /dev/null
diff --git a/src/mainboard/intel/littleplains/acpi/thermal.asl b/src/mainboard/intel/littleplains/acpi/thermal.asl
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/intel/littleplains/acpi/thermal.asl
+++ /dev/null
diff --git a/src/mainboard/intel/littleplains/acpi_tables.c b/src/mainboard/intel/littleplains/acpi_tables.c
deleted file mode 100644
index a0ebbba53c..0000000000
--- a/src/mainboard/intel/littleplains/acpi_tables.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <southbridge/intel/fsp_rangeley/nvs.h>
-#include <northbridge/intel/fsp_rangeley/northbridge.h>
-
-static global_nvs_t *gnvs_;
-
-void acpi_create_gnvs(global_nvs_t *gnvs)
-{
-	gnvs_ = gnvs;
-	memset((void *)gnvs, 0, sizeof(*gnvs));
-	gnvs->apic = 1;
-	gnvs->mpen = 1; /* Enable Multi Processing */
-	gnvs->pcnt = dev_count_cpu();
-
-	/* Enable USB ports in S3 */
-	gnvs->s3u0 = 1;
-	gnvs->s3u1 = 1;
-
-	/*
-	 * Enable Front USB ports in S5 by default
-	 * to be consistent with back port behavior
-	 */
-	gnvs->s5u0 = 1;
-	gnvs->s5u1 = 1;
-
-	/* IGD Displays */
-	gnvs->ndid = 3;
-	gnvs->did[0] = 0x80000100;
-	gnvs->did[1] = 0x80000240;
-	gnvs->did[2] = 0x80000410;
-	gnvs->did[3] = 0x80000410;
-	gnvs->did[4] = 0x00000005;
-
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* Local APICs */
-	current = acpi_create_madt_lapics(current);
-
-	/* IOAPIC */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				2, IO_APIC_ADDR, 0);
-
-	/* INT_SRC_OVR */
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
-	return current;
-}
diff --git a/src/mainboard/intel/littleplains/board_info.txt b/src/mainboard/intel/littleplains/board_info.txt
deleted file mode 100644
index f49af8aac5..0000000000
--- a/src/mainboard/intel/littleplains/board_info.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-Category: eval
-ROM protocol: SPI
-Flashrom support: y
-Release year: 2014
diff --git a/src/mainboard/intel/littleplains/cmos.layout b/src/mainboard/intel/littleplains/cmos.layout
deleted file mode 100644
index 7c623c0085..0000000000
--- a/src/mainboard/intel/littleplains/cmos.layout
+++ /dev/null
@@ -1,104 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-# -----------------------------------------------------------------
-entries
-
-# -----------------------------------------------------------------
-# Status Register A
-# -----------------------------------------------------------------
-# Status Register B
-# -----------------------------------------------------------------
-# Status Register C
-#96           4       r       0        status_c_rsvd
-#100          1       r       0        uf_flag
-#101          1       r       0        af_flag
-#102          1       r       0        pf_flag
-#103          1       r       0        irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104          7       r       0        status_d_rsvd
-#111          1       r       0        valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112          8       r       0        diag_rsvd1
-
-# -----------------------------------------------------------------
-0          120       r       0        reserved_memory
-#120        264       r       0        unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#390          2       r       0        unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-#392          3       r       0        unused
-395          4       e       6        debug_level
-#399          1       r       0        unused
-
-# coreboot config options: cpu
-400          1       e       2        hyper_threading
-#401          7       r       0        unused
-
-# coreboot config options: southbridge
-408          1       e       1        nmi
-409          2       e       7        power_on_after_fail
-#411          5       r       0        unused
-
-# MRC Scrambler Seed values
-896         32        r       0        mrc_scrambler_seed
-928         32        r       0        mrc_scrambler_seed_s3
-
-# coreboot config options: check sums
-984         16       h       0        check_sum
-#1000        24       r       0        amd_reserved
-
-#save timestamps in pre-ram boot areas
-1720        64       h       0        timestamp_value1
-1784        64       h       0        timestamp_value2
-1848        64       h       0        timestamp_value3
-1912        64       h       0        timestamp_value4
-1976        64       h       0        timestamp_value5
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     0     Emergency
-6     1     Alert
-6     2     Critical
-6     3     Error
-6     4     Warning
-6     5     Notice
-6     6     Info
-6     7     Debug
-6     8     Spew
-7     0     Disable
-7     1     Enable
-7     2     Keep
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 415 984
diff --git a/src/mainboard/intel/littleplains/config_seabios b/src/mainboard/intel/littleplains/config_seabios
deleted file mode 100644
index f688f2b530..0000000000
--- a/src/mainboard/intel/littleplains/config_seabios
+++ /dev/null
@@ -1,5 +0,0 @@
-#  The Avoton/Rangeley chip does not allow devices to write into the 0xe000
-#  segment.  This means that USB/SATA devices will not work in SeaBIOS unless
-#  we put the SeaBIOS buffer area down in the 0x9000 segment.
-
-# CONFIG_MALLOC_UPPERMEMORY is not set
diff --git a/src/mainboard/intel/littleplains/devicetree.cb b/src/mainboard/intel/littleplains/devicetree.cb
deleted file mode 100644
index 0cb73f8a02..0000000000
--- a/src/mainboard/intel/littleplains/devicetree.cb
+++ /dev/null
@@ -1,62 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2013 Sage Electronic Engineering, LLC.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-chip northbridge/intel/fsp_rangeley
-
-	device cpu_cluster 0 on
-		chip cpu/intel/fsp_model_406dx
-			device lapic 0 on end
-			# Magic APIC ID to locate this chip
-			device lapic 0xACAC off end
-
-			register "c1_battery" = "3"	# ACPI(C1) = MWAIT(C3)
-			register "c2_battery" = "4"	# ACPI(C2) = MWAIT(C6)
-			register "c3_battery" = "5"	# ACPI(C3) = MWAIT(C7)
-
-			register "c1_acpower" = "3"	# ACPI(C1) = MWAIT(C3)
-			register "c2_acpower" = "4"	# ACPI(C2) = MWAIT(C6)
-			register "c3_acpower" = "5"	# ACPI(C3) = MWAIT(C7)
-		end
-	end
-
-	device domain 0 on
-		device pci 00.0 on end # host bridge
-		device pci 1.0 on end # PCIe Port #1
-		device pci 2.0 on end # PCIe Port #2
-		device pci 3.0 on end # PCIe Port #3
-		device pci 4.0 on end # PCIe Port #4
-		chip southbridge/intel/fsp_rangeley # Rangeley SB
-
-			register "ide_legacy_combined" = "0x0"
-			register "sata_ahci" = "0x1"
-			register "sata_port_map" = "0x0f"
-
-			register "fadt_pm_profile" = "PM_DESKTOP"
-			register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE"
-
-			device pci 0b.0 on end # IQIA
-			device pci 0e.0 on end # RAS
-			device pci 13.0 on end # SMBus 1
-			device pci 14.0 on end # GbE 0
-			device pci 14.1 on end # GbE 1
-			device pci 14.2 on end # GbE 2
-			device pci 14.3 on end # GbE 3
-			device pci 16.0 on end # USB EHCI
-			device pci 17.0 on end # SATA 2.0
-			device pci 18.0 on end # SATA 3.0
-			device pci 1f.0 on end # LPC bridge
-			device pci 1f.3 on end # SMBus 0
-		end
-	end
-end
diff --git a/src/mainboard/intel/littleplains/dsdt.asl b/src/mainboard/intel/littleplains/dsdt.asl
deleted file mode 100644
index 4aad8a8b15..0000000000
--- a/src/mainboard/intel/littleplains/dsdt.asl
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	0x02,		// DSDT revision: ACPI v2.0 and up
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x20110725	// OEM revision
-)
-{
-	// Include mainboard configuration
-	#include <acpi/mainboard.asl>
-
-	// Include debug methods
-	#include <arch/x86/acpi/debug.asl>
-
-	// Some generic macros
-	#include <southbridge/intel/common/acpi/platform.asl>
-	#include "acpi/platform.asl"
-
-	// global NVS and variables
-	#include <southbridge/intel/fsp_rangeley/acpi/globalnvs.asl>
-
-	#include "acpi/thermal.asl"
-
-	#include <cpu/intel/common/acpi/cpu.asl>
-
-	Scope (\_SB) {
-		Device (PCI0)
-		{
-			#include <northbridge/intel/fsp_rangeley/acpi/rangeley.asl>
-			#include <southbridge/intel/fsp_rangeley/acpi/soc.asl>
-		}
-	}
-
-	/* Chipset specific sleep states */
-	#include <southbridge/intel/common/acpi/sleepstates.asl>
-}
diff --git a/src/mainboard/intel/littleplains/fadt.c b/src/mainboard/intel/littleplains/fadt.c
deleted file mode 100644
index 3d8db00f9f..0000000000
--- a/src/mainboard/intel/littleplains/fadt.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <southbridge/intel/fsp_rangeley/soc.h>
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
-	acpi_fill_in_fadt(fadt,facs,dsdt);
-
-#define PLATFORM_HAS_FADT_CUSTOMIZATIONS	0
-
-
-	/*
-	 * Platform specific customizations go here.
-	 * Update the #define above if customizations are added.
-	 */
-
-
-#if PLATFORM_HAS_FADT_CUSTOMIZATIONS
-	header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
-#endif
-}
diff --git a/src/mainboard/intel/littleplains/gpio.h b/src/mainboard/intel/littleplains/gpio.h
deleted file mode 100644
index 6fabe6ecec..0000000000
--- a/src/mainboard/intel/littleplains/gpio.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef LITTLEPLAINS_GPIO_H
-#define LITTLEPLAINS_GPIO_H
-
-#include <southbridge/intel/fsp_rangeley/gpio.h>
-
-/* Core GPIO */
-const struct soc_gpio soc_gpio_mode = {
-	.gpio15 = GPIO_MODE_GPIO, /* Board ID GPIO */
-	.gpio17 = GPIO_MODE_GPIO, /* Board ID GPIO */
-};
-
-const struct soc_gpio soc_gpio_direction = {
-	.gpio15 = GPIO_DIR_INPUT, /* Board ID GPIO */
-	.gpio17 = GPIO_DIR_INPUT, /* Board ID GPIO */
-};
-
-const struct soc_gpio soc_gpio_level = {
-};
-
-const struct soc_gpio soc_gpio_tpe = {
-};
-
-const struct soc_gpio soc_gpio_tne = {
-};
-
-const struct soc_gpio soc_gpio_ts = {
-};
-
-/* Keep the CFIO struct in register order, not gpio order. */
-const struct soc_cfio soc_cfio_core[] = {
-	{ 0x8000, 0x0000, 0x0004, 0x040c },  /* CFIO gpios_28 */
-	{ 0x8000, 0x0000, 0x0002, 0x040c },  /* CFIO gpios_27 */
-	{ 0x8500, 0x0000, 0x0002, 0x040c },  /* CFIO gpios_26 */
-	{ 0x8480, 0x0000, 0x0002, 0x040c },  /* CFIO gpios_21 */
-	{ 0x8480, 0x0000, 0x0002, 0x040c },  /* CFIO gpios_22 */
-	{ 0x8480, 0x0000, 0x0002, 0x040c },  /* CFIO gpios_23 */
-	{ 0x8000, 0x0000, 0x0004, 0x040c },  /* CFIO gpios_25 */
-	{ 0x8480, 0x0000, 0x0002, 0x040c },  /* CFIO gpios_24 */
-	{ 0x80c028, 0x30003, 0x0004, 0x040c },  /* CFIO gpios_19 */
-	{ 0x80c028, 0x30003, 0x0004, 0x040c },  /* CFIO gpios_20 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO gpios_18 */
-	{ 0x04a9, 0x30003, 0x0002, 0x040c },  /* CFIO gpios_17 */
-	{ 0x80c028, 0x30003, 0x0004, 0x040c },  /* CFIO gpios_7 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO gpios_4 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO gpios_5 */
-	{ 0xc528, 0x30003, 0x0002, 0x040c },  /* CFIO gpios_6 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO gpios_1 */
-	{ 0xc028, 0x20002, 0x0004, 0x040c },  /* CFIO gpios_2 */
-	{ 0xc028, 0x20002, 0x0004, 0x040c },  /* CFIO gpios_3 */
-	{ 0xc528, 0x30003, 0x0002, 0x040c },  /* CFIO gpios_0 */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO gpios_10 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO gpios_13 */
-	{ 0xc4a8, 0x30003, 0x0000, 0x040c },  /* CFIO gpios_14 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO gpios_11 */
-	{ 0xc4a8, 0x30003, 0x0000, 0x040c },  /* CFIO gpios_8 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO gpios_9 */
-	{ 0xc4a8, 0x30003, 0x0000, 0x040c },  /* CFIO gpios_12 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO gpios_29 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO gpios_30 */
-	{ 0x04a9, 0x30003, 0x0002, 0x040c },  /* CFIO gpios_15 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO gpios_16 */
-};
-
-/* SUS GPIO */
-const struct soc_gpio soc_gpio_sus_mode  = {
-	.gpio2 = GPIO_MODE_GPIO,
-	.gpio19 = GPIO_MODE_GPIO
-};
-
-const struct soc_gpio soc_gpio_sus_direction = {
-	.gpio2 = GPIO_DIR_INPUT,
-	.gpio19 = GPIO_DIR_INPUT
-};
-
-const struct soc_gpio soc_gpio_sus_level = {
-};
-
-const struct soc_gpio soc_gpio_sus_tpe = {
-};
-
-const struct soc_gpio soc_gpio_sus_tne = {
-};
-
-const struct soc_gpio soc_gpio_sus_ts = {
-};
-
-const struct soc_gpio soc_gpio_sus_we = {
-};
-
-
-/* Keep the CFIO struct in register order, not gpio order. */
-const struct soc_cfio soc_cfio_sus[] = {
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO SUS gpios_21 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO SUS gpios_20 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO SUS gpios_19 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO SUS gpios_22 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO SUS gpios_17 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO SUS gpios_18 */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO SUS gpios_14 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO SUS gpios_13 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO SUS gpios_15 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO SUS gpios_16 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO SUS gpios_25 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO SUS gpios_24 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO SUS gpios_26 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO SUS gpios_27 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO SUS gpios_23 */
-	{ 0xc4a8, 0x30003, 0x0003, 0x040c },  /* CFIO SUS gpios_2 */
-	{ 0xc4a8, 0x30003, 0x0003, 0x040c },  /* CFIO SUS gpios_1 */
-	{ 0x8050, 0x0000, 0x0004, 0x040c },  /* CFIO SUS gpios_7 */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO SUS gpios_3 */
-	{ 0xc4a8, 0x30003, 0x0003, 0x040c },  /* CFIO SUS gpios_0 */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0x8000, 0x0000, 0x0004, 0x040c },  /* CFIO SUS gpios_12 */
-	{ 0x8050, 0x0000, 0x0004, 0x040c },  /* CFIO SUS gpios_6 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO SUS gpios_10 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO SUS gpios_9 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO SUS gpios_8 */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0x8050, 0x0000, 0x0004, 0x040c },  /* CFIO SUS gpios_4 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO SUS gpios_11 */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO SUS gpios_5 */
-};
-
-const struct soc_gpio_map gpio_map = {
-	.core = {
-		.mode      = &soc_gpio_mode,
-		.direction = &soc_gpio_direction,
-		.level     = &soc_gpio_level,
-		.tpe       = &soc_gpio_tpe,
-		.tne       = &soc_gpio_tne,
-		.ts        = &soc_gpio_ts,
-		.cfio_init = &soc_cfio_core[0],
-		.cfio_entrynum = sizeof(soc_cfio_core) / sizeof(struct soc_cfio),
-	},
-	.sus = {
-		.mode      = &soc_gpio_sus_mode,
-		.direction = &soc_gpio_sus_direction,
-		.level     = &soc_gpio_sus_level,
-		.tpe       = &soc_gpio_sus_tpe,
-		.tne       = &soc_gpio_sus_tne,
-		.ts        = &soc_gpio_sus_ts,
-		.we        = &soc_gpio_sus_we,
-		.cfio_init = &soc_cfio_sus[0],
-		.cfio_entrynum = sizeof(soc_cfio_sus) / sizeof(struct soc_cfio),
-	},
-};
-
-#endif /* LITTLEPLAINS_GPIO_H */
diff --git a/src/mainboard/intel/littleplains/irq_tables.c b/src/mainboard/intel/littleplains/irq_tables.c
deleted file mode 100644
index bca68ea548..0000000000
--- a/src/mainboard/intel/littleplains/irq_tables.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- * Copyright (C) 2013, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/pirq_routing.h>
-
-#define PIRQA 0x08
-#define PIRQB 0x09
-#define PIRQC 0x0a
-#define PIRQD 0x0b
-#define PIRQE 0x0c
-#define PIRQF 0x0d
-#define PIRQG 0x0e
-#define PIRQH 0x0f
-
-#define PCI_IRQS 0xDCF0
-
-const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,  /* u32 signature */
-	PIRQ_VERSION,    /* u16 version   */
-	32+16*CONFIG_IRQ_SLOT_COUNT,	 /* There can be total 18 devices on the bus */
-	0x00,		 /* Where the interrupt router lies (bus) */
-	(0x1f << 3)|0x0,   /* Where the interrupt router lies (dev) */
-	0,		 /* IRQs devoted exclusively to PCI usage */
-	0x8086,		 /* Vendor */
-	0x0F1C,		 /* Device */
-	0,		 /* miniport */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x86,		 /* u8 checksum. */
-	{
-		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x01 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 1: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD
-		{0x00,(0x02 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 2: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD
-		{0x00,(0x03 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 3: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
-		{0x00,(0x04 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 4: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
-		{0x00,(0x0b << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // IQAT INTA-PIRQA
-		{0x00,(0x0f << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // RCEC INTA-PIRQA
-		{0x00,(0x13 << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SMBUS #1 INTA-PIRQA
-		{0x00,(0x14 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // GbE, INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
-		{0x00,(0x16 << 3)|0x0, {{PIRQH, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // EHCI INTA-PIRQH
-		{0x00,(0x17 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA2 INTA-PIRQD
-		{0x00,(0x18 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA3 INTA-PIRQD
-		{0x00,(0x1f << 3)|0x0, {{0x00, 0x0000}, {PIRQC, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC/SMBUS #0 INTB - PIRQC
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/intel/littleplains/irqroute.c b/src/mainboard/intel/littleplains/irqroute.c
deleted file mode 100644
index 2bf03cef68..0000000000
--- a/src/mainboard/intel/littleplains/irqroute.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2014 Sage Electronics Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "irqroute.h"
-
-DEFINE_IRQ_ROUTES;
diff --git a/src/mainboard/intel/littleplains/irqroute.h b/src/mainboard/intel/littleplains/irqroute.h
deleted file mode 100644
index eb44fde6cf..0000000000
--- a/src/mainboard/intel/littleplains/irqroute.h
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2014 Sage Electronics Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef IRQROUTE_H
-#define IRQROUTE_H
-
-#include <southbridge/intel/fsp_rangeley/irq.h>
-#include <southbridge/intel/fsp_rangeley/pci_devs.h>
-
-/*
- * IR01h PCIe		INT(ABCD)	- PIRQ ABCD
- * IR02h PCIe		INT(ABCD)	- PIRQ ABCD
- * IR03h PCIe		INT(ABCD)	- PIRQ ABCD
- * IR04h PCIe		INT(ABCD)	- PIRQ ABCD
- * IR0Bh IQIA		INT(ABCD)	- PIRQ EFGH
- * IR0Eh RAS		INT(A)		- PIRQ A
- * IR13h SMBUS1		INT(A)		- PIRQ B
- * IR15h GBE		INT(A)		- PIRQ CDEF
- * IR1Dh EHCI		INT(A)		- PIRQ G
- * IR13h SATA2.0	INT(A)		- PIRQ H
- * IR13h SATA3.0	INT(A)		- PIRQ A
- * IR1Fh LPC		INT(ABCD)	- PIRQ HGBC
- */
-#define PCI_DEV_PIRQ_ROUTES \
-	PCI_DEV_PIRQ_ROUTE(PCIE_PORT1_DEV,	A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(PCIE_PORT2_DEV,	D, C, B, A), \
-	PCI_DEV_PIRQ_ROUTE(PCIE_PORT3_DEV,	E, F, G, H), \
-	PCI_DEV_PIRQ_ROUTE(PCIE_PORT4_DEV,	H, G, F, E), \
-	PCI_DEV_PIRQ_ROUTE(IQAT_DEV,		E, F, G, H), \
-	PCI_DEV_PIRQ_ROUTE(HOST_BRIDGE_DEV,	H, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(RCEC_DEV,		A, A, A, B), \
-	PCI_DEV_PIRQ_ROUTE(SMBUS1_DEV,		B, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(GBE_DEV,			C, D, E, F), \
-	PCI_DEV_PIRQ_ROUTE(USB2_DEV,		G, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(SATA2_DEV,		H, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(SATA3_DEV,		A, A, A, B), \
-	PCI_DEV_PIRQ_ROUTE(PCU_DEV,			H, G, B, C)
-
-/*
- * Route each PIRQ[A-H] to a PIC IRQ[0-15]
- * Reserved: 0, 1, 2, 8, 13
- * PS2 keyboard: 12
- * ACPI/SCI: 9
- * Floppy: 6
- */
-#define PIRQ_PIC_ROUTES \
-	PIRQ_PIC(A, 10),  \
-	PIRQ_PIC(B, 11),  \
-	PIRQ_PIC(C, 10),  \
-	PIRQ_PIC(D, 11),  \
-	PIRQ_PIC(E, 14), \
-	PIRQ_PIC(F, 15), \
-	PIRQ_PIC(G, 14), \
-	PIRQ_PIC(H, 15)
-
-#endif /* IRQROUTE_H */
diff --git a/src/mainboard/intel/littleplains/romstage.c b/src/mainboard/intel/littleplains/romstage.c
deleted file mode 100644
index 08dd02de2e..0000000000
--- a/src/mainboard/intel/littleplains/romstage.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2010 coresystems GmbH
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/mmio.h>
-#include <device/pci_ops.h>
-#include <device/pci_def.h>
-#include <cpu/x86/lapic.h>
-#include <drivers/intel/fsp1_0/fsp_util.h>
-#include <southbridge/intel/fsp_rangeley/soc.h>
-#include <southbridge/intel/fsp_rangeley/gpio.h>
-#include <southbridge/intel/fsp_rangeley/romstage.h>
-#include "gpio.h"
-
-static void interrupt_routing_config(void)
-{
-	u8 *ilb_base = (u8 *)(pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf);
-
-	/*
-	* Initialize Interrupt Routings for each device in ilb_base_address.
-	* IR01 map to PCIe device 0x01 ... IR31 to device 0x1F.
-	* PIRQ_A maps to IRQ 16 ... PIRQ_H maps tp IRQ 23.
-	* This should match devicetree and the ACPI IRQ routing/
-	*/
-	write32(ilb_base + ILB_ACTL, 0x0000);  /* ACTL bit 2:0 SCIS IRQ9 */
-	write16(ilb_base + ILB_IR01, 0x3210);  /* IR01h IR(ABCD) - PIRQ(ABCD) */
-	write16(ilb_base + ILB_IR02, 0x3210);  /* IR02h IR(ABCD) - PIRQ(ABCD) */
-	write16(ilb_base + ILB_IR03, 0x7654);  /* IR03h IR(ABCD) - PIRQ(EFGH) */
-	write16(ilb_base + ILB_IR04, 0x7654);  /* IR04h IR(ABCD) - PIRQ(EFGH) */
-	write16(ilb_base + ILB_IR20, 0x7654);  /* IR14h IR(ABCD) - PIRQ(EFGH) */
-	write16(ilb_base + ILB_IR22, 0x0007);  /* IR16h IR(A) - PIRQ(H) */
-	write16(ilb_base + ILB_IR23, 0x0003);  /* IR17h IR(A) - PIRQ(D) */
-	write16(ilb_base + ILB_IR24, 0x0003);  /* IR18h IR(A) - PIRQ(D) */
-	write16(ilb_base + ILB_IR31, 0x0020);  /* IR1Fh IR(B) - PIRQ(C) */
-}
-
-/**
- * /brief mainboard call for setup that needs to be done before fsp init
- *
- */
-void early_mainboard_romstage_entry(void)
-{
-	setup_soc_gpios(&gpio_map);
-}
-
-/**
- * /brief mainboard call for setup that needs to be done after fsp init
- *
- */
-void late_mainboard_romstage_entry(void)
-{
-	interrupt_routing_config();
-}
-
-/**
- * Get function disables - most of these will be done automatically
- * @param mask pointer to the function-disable bitfield
- */
-void get_func_disables(uint32_t *mask)
-{
-
-}
-
-void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
-{
-	/* No overrides needed */
-	return;
-}
diff --git a/src/mainboard/intel/littleplains/thermal.h b/src/mainboard/intel/littleplains/thermal.h
deleted file mode 100644
index 14f5fa7dd2..0000000000
--- a/src/mainboard/intel/littleplains/thermal.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef LITTLEPLAINS_THERMAL_H
-#define LITTLEPLAINS_THERMAL_H
-
-
-/* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE	100
-
-/* Temperature which OS will throttle CPU */
-#define PASSIVE_TEMPERATURE	90
-
-/* Tj_max value for calculating PECI CPU temperature */
-#define MAX_TEMPERATURE		100
-
-#endif
diff --git a/src/mainboard/intel/mohonpeak/Kconfig b/src/mainboard/intel/mohonpeak/Kconfig
deleted file mode 100644
index de91ca4835..0000000000
--- a/src/mainboard/intel/mohonpeak/Kconfig
+++ /dev/null
@@ -1,76 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-if BOARD_INTEL_MOHONPEAK
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select NORTHBRIDGE_INTEL_FSP_RANGELEY
-	select SOUTHBRIDGE_INTEL_FSP_RANGELEY
-	select BOARD_ROMSIZE_KB_2048 #actual chip is 8MB
-	select HAVE_ACPI_TABLES
-	select HAVE_OPTION_TABLE
-	select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT
-
-config MAINBOARD_DIR
-	string
-	default intel/mohonpeak
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Mohon Peak CRB"
-
-config MAX_CPUS
-	int
-	default 16
-
-config FSP_FILE
-	string
-	default "../intel/fsp/rangeley/FvFsp.bin"
-
-config CBFS_SIZE
-	hex
-	default 0x00200000
-
-config ENABLE_FSP_FAST_BOOT
-	bool
-	depends on HAVE_FSP_BIN
-	default y
-
-config VIRTUAL_ROM_SIZE
-	hex
-	depends on ENABLE_FSP_FAST_BOOT
-	default 0x400000
-
-config FSP_PACKAGE_DEFAULT
-	bool "Configure defaults for the Intel FSP package"
-	default n
-
-config UART_FOR_CONSOLE
-	int
-	default 1
-	help
-	  The Mohon Peak board uses COM2 (2f8) for the serial console.
-
-config PAYLOAD_CONFIGFILE
-	string
-	depends on PAYLOAD_SEABIOS
-	default "$(top)/src/mainboard/$(MAINBOARDDIR)/config_seabios"
-	help
-	  The Avoton/Rangeley chip does not allow devices to write into the 0xe000
-	  segment.  This means that USB/SATA devices will not work in SeaBIOS unless
-	  we put the SeaBIOS buffer area down in the 0x9000 segment.
-
-endif # BOARD_INTEL_MOHONPEAK
diff --git a/src/mainboard/intel/mohonpeak/Kconfig.name b/src/mainboard/intel/mohonpeak/Kconfig.name
deleted file mode 100644
index 2fc6540d06..0000000000
--- a/src/mainboard/intel/mohonpeak/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_INTEL_MOHONPEAK
-	bool "Mohon Peak CRB"
diff --git a/src/mainboard/intel/mohonpeak/Makefile.inc b/src/mainboard/intel/mohonpeak/Makefile.inc
deleted file mode 100644
index c34ef4b006..0000000000
--- a/src/mainboard/intel/mohonpeak/Makefile.inc
+++ /dev/null
@@ -1,16 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2014 Sage Electronics Engineering, LLC.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-ramstage-y += irqroute.c
diff --git a/src/mainboard/intel/mohonpeak/acpi/ec.asl b/src/mainboard/intel/mohonpeak/acpi/ec.asl
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/intel/mohonpeak/acpi/ec.asl
+++ /dev/null
diff --git a/src/mainboard/intel/mohonpeak/acpi/mainboard.asl b/src/mainboard/intel/mohonpeak/acpi/mainboard.asl
deleted file mode 100644
index aecc2b6905..0000000000
--- a/src/mainboard/intel/mohonpeak/acpi/mainboard.asl
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-// #define ACPI_INCLUDE_PMIO 1 /* uncomment to enable PMIO block in soc.asl */
-// #define ACPI_INCLUDE_GPIO 1 /* uncomment to enable GPIO block in soc.asl */
-
-Device (PWRB)
-{
-	Name(_HID, EisaId("PNP0C0C"))
-
-	// Wake
-	Name(_PRW, Package(){0x1d, 0x05})
-}
diff --git a/src/mainboard/intel/mohonpeak/acpi/platform.asl b/src/mainboard/intel/mohonpeak/acpi/platform.asl
deleted file mode 100644
index 059cd740ff..0000000000
--- a/src/mainboard/intel/mohonpeak/acpi/platform.asl
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/* The _WAK method is called on system wakeup */
-
-Method(_WAK,1)
-{
-	Return(Package(){0,0})
-}
diff --git a/src/mainboard/intel/mohonpeak/acpi/superio.asl b/src/mainboard/intel/mohonpeak/acpi/superio.asl
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/intel/mohonpeak/acpi/superio.asl
+++ /dev/null
diff --git a/src/mainboard/intel/mohonpeak/acpi/thermal.asl b/src/mainboard/intel/mohonpeak/acpi/thermal.asl
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/intel/mohonpeak/acpi/thermal.asl
+++ /dev/null
diff --git a/src/mainboard/intel/mohonpeak/acpi_tables.c b/src/mainboard/intel/mohonpeak/acpi_tables.c
deleted file mode 100644
index a0ebbba53c..0000000000
--- a/src/mainboard/intel/mohonpeak/acpi_tables.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <southbridge/intel/fsp_rangeley/nvs.h>
-#include <northbridge/intel/fsp_rangeley/northbridge.h>
-
-static global_nvs_t *gnvs_;
-
-void acpi_create_gnvs(global_nvs_t *gnvs)
-{
-	gnvs_ = gnvs;
-	memset((void *)gnvs, 0, sizeof(*gnvs));
-	gnvs->apic = 1;
-	gnvs->mpen = 1; /* Enable Multi Processing */
-	gnvs->pcnt = dev_count_cpu();
-
-	/* Enable USB ports in S3 */
-	gnvs->s3u0 = 1;
-	gnvs->s3u1 = 1;
-
-	/*
-	 * Enable Front USB ports in S5 by default
-	 * to be consistent with back port behavior
-	 */
-	gnvs->s5u0 = 1;
-	gnvs->s5u1 = 1;
-
-	/* IGD Displays */
-	gnvs->ndid = 3;
-	gnvs->did[0] = 0x80000100;
-	gnvs->did[1] = 0x80000240;
-	gnvs->did[2] = 0x80000410;
-	gnvs->did[3] = 0x80000410;
-	gnvs->did[4] = 0x00000005;
-
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* Local APICs */
-	current = acpi_create_madt_lapics(current);
-
-	/* IOAPIC */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				2, IO_APIC_ADDR, 0);
-
-	/* INT_SRC_OVR */
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 0, 2, 0);
-	current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
-		 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
-
-	return current;
-}
diff --git a/src/mainboard/intel/mohonpeak/board_info.txt b/src/mainboard/intel/mohonpeak/board_info.txt
deleted file mode 100644
index f49af8aac5..0000000000
--- a/src/mainboard/intel/mohonpeak/board_info.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-Category: eval
-ROM protocol: SPI
-Flashrom support: y
-Release year: 2014
diff --git a/src/mainboard/intel/mohonpeak/cmos.layout b/src/mainboard/intel/mohonpeak/cmos.layout
deleted file mode 100644
index 7c623c0085..0000000000
--- a/src/mainboard/intel/mohonpeak/cmos.layout
+++ /dev/null
@@ -1,104 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-# -----------------------------------------------------------------
-entries
-
-# -----------------------------------------------------------------
-# Status Register A
-# -----------------------------------------------------------------
-# Status Register B
-# -----------------------------------------------------------------
-# Status Register C
-#96           4       r       0        status_c_rsvd
-#100          1       r       0        uf_flag
-#101          1       r       0        af_flag
-#102          1       r       0        pf_flag
-#103          1       r       0        irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104          7       r       0        status_d_rsvd
-#111          1       r       0        valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112          8       r       0        diag_rsvd1
-
-# -----------------------------------------------------------------
-0          120       r       0        reserved_memory
-#120        264       r       0        unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#390          2       r       0        unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-#392          3       r       0        unused
-395          4       e       6        debug_level
-#399          1       r       0        unused
-
-# coreboot config options: cpu
-400          1       e       2        hyper_threading
-#401          7       r       0        unused
-
-# coreboot config options: southbridge
-408          1       e       1        nmi
-409          2       e       7        power_on_after_fail
-#411          5       r       0        unused
-
-# MRC Scrambler Seed values
-896         32        r       0        mrc_scrambler_seed
-928         32        r       0        mrc_scrambler_seed_s3
-
-# coreboot config options: check sums
-984         16       h       0        check_sum
-#1000        24       r       0        amd_reserved
-
-#save timestamps in pre-ram boot areas
-1720        64       h       0        timestamp_value1
-1784        64       h       0        timestamp_value2
-1848        64       h       0        timestamp_value3
-1912        64       h       0        timestamp_value4
-1976        64       h       0        timestamp_value5
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     0     Emergency
-6     1     Alert
-6     2     Critical
-6     3     Error
-6     4     Warning
-6     5     Notice
-6     6     Info
-6     7     Debug
-6     8     Spew
-7     0     Disable
-7     1     Enable
-7     2     Keep
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 415 984
diff --git a/src/mainboard/intel/mohonpeak/config_seabios b/src/mainboard/intel/mohonpeak/config_seabios
deleted file mode 100644
index f688f2b530..0000000000
--- a/src/mainboard/intel/mohonpeak/config_seabios
+++ /dev/null
@@ -1,5 +0,0 @@
-#  The Avoton/Rangeley chip does not allow devices to write into the 0xe000
-#  segment.  This means that USB/SATA devices will not work in SeaBIOS unless
-#  we put the SeaBIOS buffer area down in the 0x9000 segment.
-
-# CONFIG_MALLOC_UPPERMEMORY is not set
diff --git a/src/mainboard/intel/mohonpeak/devicetree.cb b/src/mainboard/intel/mohonpeak/devicetree.cb
deleted file mode 100644
index 0cb73f8a02..0000000000
--- a/src/mainboard/intel/mohonpeak/devicetree.cb
+++ /dev/null
@@ -1,62 +0,0 @@
-#
-# This file is part of the coreboot project.
-#
-# Copyright (C) 2013 Sage Electronic Engineering, LLC.
-#
-# This program is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; version 2 of the License.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-chip northbridge/intel/fsp_rangeley
-
-	device cpu_cluster 0 on
-		chip cpu/intel/fsp_model_406dx
-			device lapic 0 on end
-			# Magic APIC ID to locate this chip
-			device lapic 0xACAC off end
-
-			register "c1_battery" = "3"	# ACPI(C1) = MWAIT(C3)
-			register "c2_battery" = "4"	# ACPI(C2) = MWAIT(C6)
-			register "c3_battery" = "5"	# ACPI(C3) = MWAIT(C7)
-
-			register "c1_acpower" = "3"	# ACPI(C1) = MWAIT(C3)
-			register "c2_acpower" = "4"	# ACPI(C2) = MWAIT(C6)
-			register "c3_acpower" = "5"	# ACPI(C3) = MWAIT(C7)
-		end
-	end
-
-	device domain 0 on
-		device pci 00.0 on end # host bridge
-		device pci 1.0 on end # PCIe Port #1
-		device pci 2.0 on end # PCIe Port #2
-		device pci 3.0 on end # PCIe Port #3
-		device pci 4.0 on end # PCIe Port #4
-		chip southbridge/intel/fsp_rangeley # Rangeley SB
-
-			register "ide_legacy_combined" = "0x0"
-			register "sata_ahci" = "0x1"
-			register "sata_port_map" = "0x0f"
-
-			register "fadt_pm_profile" = "PM_DESKTOP"
-			register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE"
-
-			device pci 0b.0 on end # IQIA
-			device pci 0e.0 on end # RAS
-			device pci 13.0 on end # SMBus 1
-			device pci 14.0 on end # GbE 0
-			device pci 14.1 on end # GbE 1
-			device pci 14.2 on end # GbE 2
-			device pci 14.3 on end # GbE 3
-			device pci 16.0 on end # USB EHCI
-			device pci 17.0 on end # SATA 2.0
-			device pci 18.0 on end # SATA 3.0
-			device pci 1f.0 on end # LPC bridge
-			device pci 1f.3 on end # SMBus 0
-		end
-	end
-end
diff --git a/src/mainboard/intel/mohonpeak/dsdt.asl b/src/mainboard/intel/mohonpeak/dsdt.asl
deleted file mode 100644
index 4aad8a8b15..0000000000
--- a/src/mainboard/intel/mohonpeak/dsdt.asl
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	0x02,		// DSDT revision: ACPI v2.0 and up
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x20110725	// OEM revision
-)
-{
-	// Include mainboard configuration
-	#include <acpi/mainboard.asl>
-
-	// Include debug methods
-	#include <arch/x86/acpi/debug.asl>
-
-	// Some generic macros
-	#include <southbridge/intel/common/acpi/platform.asl>
-	#include "acpi/platform.asl"
-
-	// global NVS and variables
-	#include <southbridge/intel/fsp_rangeley/acpi/globalnvs.asl>
-
-	#include "acpi/thermal.asl"
-
-	#include <cpu/intel/common/acpi/cpu.asl>
-
-	Scope (\_SB) {
-		Device (PCI0)
-		{
-			#include <northbridge/intel/fsp_rangeley/acpi/rangeley.asl>
-			#include <southbridge/intel/fsp_rangeley/acpi/soc.asl>
-		}
-	}
-
-	/* Chipset specific sleep states */
-	#include <southbridge/intel/common/acpi/sleepstates.asl>
-}
diff --git a/src/mainboard/intel/mohonpeak/fadt.c b/src/mainboard/intel/mohonpeak/fadt.c
deleted file mode 100644
index 3d8db00f9f..0000000000
--- a/src/mainboard/intel/mohonpeak/fadt.c
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-#include <southbridge/intel/fsp_rangeley/soc.h>
-
-void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
-{
-	acpi_fill_in_fadt(fadt,facs,dsdt);
-
-#define PLATFORM_HAS_FADT_CUSTOMIZATIONS	0
-
-
-	/*
-	 * Platform specific customizations go here.
-	 * Update the #define above if customizations are added.
-	 */
-
-
-#if PLATFORM_HAS_FADT_CUSTOMIZATIONS
-	header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
-#endif
-}
diff --git a/src/mainboard/intel/mohonpeak/gpio.h b/src/mainboard/intel/mohonpeak/gpio.h
deleted file mode 100644
index 29eb75e4b9..0000000000
--- a/src/mainboard/intel/mohonpeak/gpio.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef MOHONPEAK_GPIO_H
-#define MOHONPEAK_GPIO_H
-
-#include <southbridge/intel/fsp_rangeley/gpio.h>
-
-/* Core GPIO */
-const struct soc_gpio soc_gpio_mode = {
-	.gpio15 = GPIO_MODE_GPIO, /* Board ID GPIO */
-	.gpio17 = GPIO_MODE_GPIO, /* Board ID GPIO */
-};
-
-const struct soc_gpio soc_gpio_direction = {
-	.gpio15 = GPIO_DIR_INPUT, /* Board ID GPIO */
-	.gpio17 = GPIO_DIR_INPUT, /* Board ID GPIO */
-};
-
-const struct soc_gpio soc_gpio_level = {
-};
-
-const struct soc_gpio soc_gpio_tpe = {
-};
-
-const struct soc_gpio soc_gpio_tne = {
-};
-
-const struct soc_gpio soc_gpio_ts = {
-};
-
-/* Keep the CFIO struct in register order, not gpio order. */
-const struct soc_cfio soc_cfio_core[] = {
-	{ 0x8000, 0x0000, 0x0004, 0x040c },  /* CFIO gpios_28 */
-	{ 0x8000, 0x0000, 0x0002, 0x040c },  /* CFIO gpios_27 */
-	{ 0x8500, 0x0000, 0x0002, 0x040c },  /* CFIO gpios_26 */
-	{ 0x8480, 0x0000, 0x0002, 0x040c },  /* CFIO gpios_21 */
-	{ 0x8480, 0x0000, 0x0002, 0x040c },  /* CFIO gpios_22 */
-	{ 0x8480, 0x0000, 0x0002, 0x040c },  /* CFIO gpios_23 */
-	{ 0x8000, 0x0000, 0x0004, 0x040c },  /* CFIO gpios_25 */
-	{ 0x8480, 0x0000, 0x0002, 0x040c },  /* CFIO gpios_24 */
-	{ 0x80c028, 0x30003, 0x0004, 0x040c },  /* CFIO gpios_19 */
-	{ 0x80c028, 0x30003, 0x0004, 0x040c },  /* CFIO gpios_20 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO gpios_18 */
-	{ 0x04a9, 0x30003, 0x0002, 0x040c },  /* CFIO gpios_17 */
-	{ 0x80c028, 0x30003, 0x0004, 0x040c },  /* CFIO gpios_7 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO gpios_4 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO gpios_5 */
-	{ 0xc528, 0x30003, 0x0002, 0x040c },  /* CFIO gpios_6 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO gpios_1 */
-	{ 0xc028, 0x20002, 0x0004, 0x040c },  /* CFIO gpios_2 */
-	{ 0xc028, 0x20002, 0x0004, 0x040c },  /* CFIO gpios_3 */
-	{ 0xc528, 0x30003, 0x0002, 0x040c },  /* CFIO gpios_0 */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO gpios_10 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO gpios_13 */
-	{ 0xc4a8, 0x30003, 0x0000, 0x040c },  /* CFIO gpios_14 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO gpios_11 */
-	{ 0xc4a8, 0x30003, 0x0000, 0x040c },  /* CFIO gpios_8 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO gpios_9 */
-	{ 0xc4a8, 0x30003, 0x0000, 0x040c },  /* CFIO gpios_12 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO gpios_29 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO gpios_30 */
-	{ 0x04a9, 0x30003, 0x0002, 0x040c },  /* CFIO gpios_15 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO gpios_16 */
-};
-
-/* SUS GPIO */
-const struct soc_gpio soc_gpio_sus_mode  = {
-	.gpio2 = GPIO_MODE_GPIO,
-};
-
-const struct soc_gpio soc_gpio_sus_direction = {
-	.gpio2 = GPIO_DIR_INPUT,
-};
-
-const struct soc_gpio soc_gpio_sus_level = {
-};
-
-const struct soc_gpio soc_gpio_sus_tpe = {
-};
-
-const struct soc_gpio soc_gpio_sus_tne = {
-};
-
-const struct soc_gpio soc_gpio_sus_ts = {
-};
-
-const struct soc_gpio soc_gpio_sus_we = {
-};
-
-
-/* Keep the CFIO struct in register order, not gpio order. */
-const struct soc_cfio soc_cfio_sus[] = {
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO SUS gpios_21 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO SUS gpios_20 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO SUS gpios_19 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO SUS gpios_22 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO SUS gpios_17 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO SUS gpios_18 */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO SUS gpios_14 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO SUS gpios_13 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO SUS gpios_15 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO SUS gpios_16 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO SUS gpios_25 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO SUS gpios_24 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO SUS gpios_26 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO SUS gpios_27 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO SUS gpios_23 */
-	{ 0xc4a8, 0x30003, 0x0003, 0x040c },  /* CFIO SUS gpios_2 */
-	{ 0xc4a8, 0x30003, 0x0003, 0x040c },  /* CFIO SUS gpios_1 */
-	{ 0x8050, 0x0000, 0x0004, 0x040c },  /* CFIO SUS gpios_7 */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO SUS gpios_3 */
-	{ 0xc4a8, 0x30003, 0x0003, 0x040c },  /* CFIO SUS gpios_0 */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0x8000, 0x0000, 0x0004, 0x040c },  /* CFIO SUS gpios_12 */
-	{ 0x8050, 0x0000, 0x0004, 0x040c },  /* CFIO SUS gpios_6 */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO SUS gpios_10 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO SUS gpios_9 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO SUS gpios_8 */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0x8050, 0x0000, 0x0004, 0x040c },  /* CFIO SUS gpios_4 */
-	{ 0xc4a8, 0x30003, 0x0002, 0x040c },  /* CFIO SUS gpios_11 */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0x0000, 0x0000, 0x0000, 0x0000 },  /* CFIO Reserved */
-	{ 0xc028, 0x30003, 0x0004, 0x040c },  /* CFIO SUS gpios_5 */
-};
-
-const struct soc_gpio_map gpio_map = {
-	.core = {
-		.mode      = &soc_gpio_mode,
-		.direction = &soc_gpio_direction,
-		.level     = &soc_gpio_level,
-		.tpe       = &soc_gpio_tpe,
-		.tne       = &soc_gpio_tne,
-		.ts        = &soc_gpio_ts,
-		.cfio_init = &soc_cfio_core[0],
-		.cfio_entrynum = sizeof(soc_cfio_core) / sizeof(struct soc_cfio),
-	},
-	.sus = {
-		.mode      = &soc_gpio_sus_mode,
-		.direction = &soc_gpio_sus_direction,
-		.level     = &soc_gpio_sus_level,
-		.tpe       = &soc_gpio_sus_tpe,
-		.tne       = &soc_gpio_sus_tne,
-		.ts        = &soc_gpio_sus_ts,
-		.we        = &soc_gpio_sus_we,
-		.cfio_init = &soc_cfio_sus[0],
-		.cfio_entrynum = sizeof(soc_cfio_sus) / sizeof(struct soc_cfio),
-	},
-};
-
-#endif /* MOHONPEAK_GPIO_H */
diff --git a/src/mainboard/intel/mohonpeak/irq_tables.c b/src/mainboard/intel/mohonpeak/irq_tables.c
deleted file mode 100644
index bca68ea548..0000000000
--- a/src/mainboard/intel/mohonpeak/irq_tables.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- * Copyright (C) 2013, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/pirq_routing.h>
-
-#define PIRQA 0x08
-#define PIRQB 0x09
-#define PIRQC 0x0a
-#define PIRQD 0x0b
-#define PIRQE 0x0c
-#define PIRQF 0x0d
-#define PIRQG 0x0e
-#define PIRQH 0x0f
-
-#define PCI_IRQS 0xDCF0
-
-const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,  /* u32 signature */
-	PIRQ_VERSION,    /* u16 version   */
-	32+16*CONFIG_IRQ_SLOT_COUNT,	 /* There can be total 18 devices on the bus */
-	0x00,		 /* Where the interrupt router lies (bus) */
-	(0x1f << 3)|0x0,   /* Where the interrupt router lies (dev) */
-	0,		 /* IRQs devoted exclusively to PCI usage */
-	0x8086,		 /* Vendor */
-	0x0F1C,		 /* Device */
-	0,		 /* miniport */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-	0x86,		 /* u8 checksum. */
-	{
-		/* bus,       dev|fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */
-		{0x00,(0x01 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 1: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD
-		{0x00,(0x02 << 3)|0x0, {{PIRQA, PCI_IRQS}, {PIRQB, PCI_IRQS}, {PIRQC, PCI_IRQS}, {PIRQD, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 2: INTA-PIRQA, INTB-PIRQB, INTC-PIRQC, INTD-PIRQD
-		{0x00,(0x03 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 3: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
-		{0x00,(0x04 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // PCIE Port 4: INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
-		{0x00,(0x0b << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // IQAT INTA-PIRQA
-		{0x00,(0x0f << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // RCEC INTA-PIRQA
-		{0x00,(0x13 << 3)|0x0, {{PIRQA, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SMBUS #1 INTA-PIRQA
-		{0x00,(0x14 << 3)|0x0, {{PIRQE, PCI_IRQS}, {PIRQF, PCI_IRQS}, {PIRQG, PCI_IRQS}, {PIRQH, PCI_IRQS}}, 0x0, 0x0}, // GbE, INTA-PIRQE, INTB-PIRQF, INTC-PIRQG, INTD-PIRQH
-		{0x00,(0x16 << 3)|0x0, {{PIRQH, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // EHCI INTA-PIRQH
-		{0x00,(0x17 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA2 INTA-PIRQD
-		{0x00,(0x18 << 3)|0x0, {{PIRQD, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // SATA3 INTA-PIRQD
-		{0x00,(0x1f << 3)|0x0, {{0x00, 0x0000}, {PIRQC, PCI_IRQS}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0}, // LPC/SMBUS #0 INTB - PIRQC
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/intel/mohonpeak/irqroute.c b/src/mainboard/intel/mohonpeak/irqroute.c
deleted file mode 100644
index 2bf03cef68..0000000000
--- a/src/mainboard/intel/mohonpeak/irqroute.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2014 Sage Electronics Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "irqroute.h"
-
-DEFINE_IRQ_ROUTES;
diff --git a/src/mainboard/intel/mohonpeak/irqroute.h b/src/mainboard/intel/mohonpeak/irqroute.h
deleted file mode 100644
index 43a69d9620..0000000000
--- a/src/mainboard/intel/mohonpeak/irqroute.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2014 Sage Electronics Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef IRQROUTE_H
-#define IRQROUTE_H
-
-#include <southbridge/intel/fsp_rangeley/irq.h>
-#include <southbridge/intel/fsp_rangeley/pci_devs.h>
-
-/*
- * IR01h PCIe		INT(ABCD)	- PIRQ ABCD
- * IR02h PCIe		INT(ABCD)	- PIRQ ABCD
- * IR03h PCIe		INT(ABCD)	- PIRQ ABCD
- * IR04h PCIe		INT(ABCD)	- PIRQ ABCD
- * IR0Bh IQIA		INT(ABCD)	- PIRQ EFGH
- * IR0Eh RAS		INT(A)		- PIRQ A
- * IR13h SMBUS1		INT(A)		- PIRQ B
- * IR15h GBE		INT(A)		- PIRQ CDEF
- * IR1Dh EHCI		INT(A)		- PIRQ G
- * IR13h SATA2.0	INT(A)		- PIRQ H
- * IR13h SATA3.0	INT(A)		- PIRQ A
- * IR1Fh LPC		INT(ABCD)	- PIRQ HGBC
- */
-
- /* Devices set as A, A, A, A evaluate as 0, and don't get set */
-#define PCI_DEV_PIRQ_ROUTES \
-	PCI_DEV_PIRQ_ROUTE(PCIE_PORT1_DEV,	A, B, C, D), \
-	PCI_DEV_PIRQ_ROUTE(PCIE_PORT2_DEV,	D, C, B, A), \
-	PCI_DEV_PIRQ_ROUTE(PCIE_PORT3_DEV,	E, F, G, H), \
-	PCI_DEV_PIRQ_ROUTE(PCIE_PORT4_DEV,	H, G, F, E), \
-	PCI_DEV_PIRQ_ROUTE(IQAT_DEV,		E, F, G, H), \
-	PCI_DEV_PIRQ_ROUTE(HOST_BRIDGE_DEV,	H, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(RCEC_DEV,		A, A, A, B), \
-	PCI_DEV_PIRQ_ROUTE(SMBUS1_DEV,		B, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(GBE_DEV,			C, D, E, F), \
-	PCI_DEV_PIRQ_ROUTE(USB2_DEV,		G, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(SATA2_DEV,		H, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(SATA3_DEV,		A, A, A, B), \
-	PCI_DEV_PIRQ_ROUTE(PCU_DEV,			H, G, B, C)
-
-/*
- * Route each PIRQ[A-H] to a PIC IRQ[0-15]
- * Reserved: 0, 1, 2, 8, 13
- * PS2 keyboard: 12
- * ACPI/SCI: 9
- * Floppy: 6
- */
-#define PIRQ_PIC_ROUTES \
-	PIRQ_PIC(A, 10),  \
-	PIRQ_PIC(B, 11),  \
-	PIRQ_PIC(C, 10),  \
-	PIRQ_PIC(D, 11),  \
-	PIRQ_PIC(E, 14), \
-	PIRQ_PIC(F, 15), \
-	PIRQ_PIC(G, 14), \
-	PIRQ_PIC(H, 15)
-
-#endif /* IRQROUTE_H */
diff --git a/src/mainboard/intel/mohonpeak/romstage.c b/src/mainboard/intel/mohonpeak/romstage.c
deleted file mode 100644
index 08dd02de2e..0000000000
--- a/src/mainboard/intel/mohonpeak/romstage.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2010 coresystems GmbH
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/mmio.h>
-#include <device/pci_ops.h>
-#include <device/pci_def.h>
-#include <cpu/x86/lapic.h>
-#include <drivers/intel/fsp1_0/fsp_util.h>
-#include <southbridge/intel/fsp_rangeley/soc.h>
-#include <southbridge/intel/fsp_rangeley/gpio.h>
-#include <southbridge/intel/fsp_rangeley/romstage.h>
-#include "gpio.h"
-
-static void interrupt_routing_config(void)
-{
-	u8 *ilb_base = (u8 *)(pci_read_config32(SOC_LPC_DEV, IBASE) & ~0xf);
-
-	/*
-	* Initialize Interrupt Routings for each device in ilb_base_address.
-	* IR01 map to PCIe device 0x01 ... IR31 to device 0x1F.
-	* PIRQ_A maps to IRQ 16 ... PIRQ_H maps tp IRQ 23.
-	* This should match devicetree and the ACPI IRQ routing/
-	*/
-	write32(ilb_base + ILB_ACTL, 0x0000);  /* ACTL bit 2:0 SCIS IRQ9 */
-	write16(ilb_base + ILB_IR01, 0x3210);  /* IR01h IR(ABCD) - PIRQ(ABCD) */
-	write16(ilb_base + ILB_IR02, 0x3210);  /* IR02h IR(ABCD) - PIRQ(ABCD) */
-	write16(ilb_base + ILB_IR03, 0x7654);  /* IR03h IR(ABCD) - PIRQ(EFGH) */
-	write16(ilb_base + ILB_IR04, 0x7654);  /* IR04h IR(ABCD) - PIRQ(EFGH) */
-	write16(ilb_base + ILB_IR20, 0x7654);  /* IR14h IR(ABCD) - PIRQ(EFGH) */
-	write16(ilb_base + ILB_IR22, 0x0007);  /* IR16h IR(A) - PIRQ(H) */
-	write16(ilb_base + ILB_IR23, 0x0003);  /* IR17h IR(A) - PIRQ(D) */
-	write16(ilb_base + ILB_IR24, 0x0003);  /* IR18h IR(A) - PIRQ(D) */
-	write16(ilb_base + ILB_IR31, 0x0020);  /* IR1Fh IR(B) - PIRQ(C) */
-}
-
-/**
- * /brief mainboard call for setup that needs to be done before fsp init
- *
- */
-void early_mainboard_romstage_entry(void)
-{
-	setup_soc_gpios(&gpio_map);
-}
-
-/**
- * /brief mainboard call for setup that needs to be done after fsp init
- *
- */
-void late_mainboard_romstage_entry(void)
-{
-	interrupt_routing_config();
-}
-
-/**
- * Get function disables - most of these will be done automatically
- * @param mask pointer to the function-disable bitfield
- */
-void get_func_disables(uint32_t *mask)
-{
-
-}
-
-void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
-{
-	/* No overrides needed */
-	return;
-}
diff --git a/src/mainboard/intel/mohonpeak/thermal.h b/src/mainboard/intel/mohonpeak/thermal.h
deleted file mode 100644
index cc95fdb0c6..0000000000
--- a/src/mainboard/intel/mohonpeak/thermal.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef MOHONPEAK_THERMAL_H
-#define MOHONPEAK_THERMAL_H
-
-
-/* Temperature which OS will shutdown at */
-#define CRITICAL_TEMPERATURE	100
-
-/* Temperature which OS will throttle CPU */
-#define PASSIVE_TEMPERATURE	90
-
-/* Tj_max value for calculating PECI CPU temperature */
-#define MAX_TEMPERATURE		100
-
-#endif