diff options
| author | Martin Roth <martin.roth@se-eng.com> | 2014-10-28 18:57:48 -0600 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-10-29 15:30:16 +0100 |
| commit | 21c48d27dde60fe73cf0e57ae64a473541461a20 (patch) | |
| tree | e9dc5e0e4032454141c4a9297633fb7f4ea957e2 /src/mainboard/intel | |
| parent | cab9efb2be41ffbc2e6d97b2994915d8de2ccd84 (diff) | |
minnowmax: Tell the FSP to set TSEG to 8MB
Minnowboard Max was broken by
commit 454625c5 - intel/fsp_baytrail: Fix SMM/SMI
because TSEG wasn't set to 8MB by the FSP.
The default in the FSP is 1MB.
Change-Id: I2e671a6ca0240e931399920c62439c36133789aa
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7240
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/minnowmax/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb index 4e3833ecbc..a0ac7ae74a 100644 --- a/src/mainboard/intel/minnowmax/devicetree.cb +++ b/src/mainboard/intel/minnowmax/devicetree.cb @@ -27,7 +27,7 @@ chip soc/intel/fsp_baytrail register "SataMode" = "SATA_MODE_AHCI" register "MrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" register "MrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" - register "MrcInitTsegSize" = "TSEG_SIZE_DEFAULT" + register "MrcInitTsegSize" = "TSEG_SIZE_8_MB" register "MrcInitMmioSize" = "MMIO_SIZE_DEFAULT" register "eMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" register "IgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" |