soc/intel/alderlake: Enable Irms UPD for ADL

This change sets Irms config in FSP if TdcTimeWindow and TdcCurrentLimit
is set to non zero. It results VR TDC Input current to be treated as it
is root mean square.

This change also optimizes the check of TdcTimeWindow and TdcCurrentLimit
for TdcEnable UPD.

BRANCH=None
TEST=Build and boot brya with debug FSP and verify Irms UPD value
from logs

Change-Id: Ice5c775ef9560503109957a1ed994af1d287aafc
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>

0 files changed, 0 insertions, 0 deletions