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authorWonkyu Kim <wonkyu.kim@intel.com>2020-05-05 09:10:13 -0700
committerPatrick Georgi <pgeorgi@google.com>2020-05-26 15:09:50 +0000
commit165efa1b863ad8c35646beda6ddd76075c5674a2 (patch)
tree66b940b7aebb07ba462d60ae822a938bc2d70f4a /src/mainboard/intel
parentf381d97856854a4b43c0acdae9aaff991837ce64 (diff)
soc/intel/tigerlake: Disable VMD
It's already disabled by FSP default but disable VMD by devicetree to remove dependency with FSP default setting. BUG=None Branch=None Test=Build TGLRVP and boot up and check FSP log for checking VMD is disabled. Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ief81fe481b94abed9754881cf1f454999fafa52e Reviewed-on: https://review.coreboot.org/c/coreboot/+/41061 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb2
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb2
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index 24cc907da7..7669b183fc 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -164,7 +164,7 @@ chip soc/intel/tigerlake
device pci 0d.1 on end # USB xDCI (OTG) 0x9A15
device pci 0d.2 off end # TBT DMA0 0x9A1B
device pci 0d.3 off end # TBT DMA1 0x9A1D
- device pci 0e.0 on end # VMD 0x9A0B
+ device pci 0e.0 off end # VMD 0x9A0B
# From PCH EDS(576591)
device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index eb6814e5bf..1d1d6dc633 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -160,7 +160,7 @@ chip soc/intel/tigerlake
device pci 0d.1 on end # USB xDCI (OTG) 0x9A15
device pci 0d.2 off end # TBT DMA0 0x9A1B
device pci 0d.3 off end # TBT DMA1 0x9A1D
- device pci 0e.0 on end # VMD 0x9A0B
+ device pci 0e.0 off end # VMD 0x9A0B
# From PCH EDS(576591)
device pci 10.2 off end # CNVi: BT 0xA0F5 - A0F7