diff options
| author | Tan, Lean Sheng <lean.sheng.tan@intel.com> | 2021-05-26 06:40:56 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-06-01 05:58:39 +0000 |
| commit | 09133c78dd2c5753802bcf5b7e7eb9b5be9ecf6d (patch) | |
| tree | 72bd269e79922481dc71c7c81606836609a8ffa0 /src/mainboard/intel | |
| parent | cdb81500f1fbfef2865e692e1193e39a56f9bca2 (diff) | |
soc/intel/elkhartlake: Update FSP-S UPD LPSS related configs
Add Silicon upd settings for LPSS (GSPI/UART/I2C).
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ib0c3cd1d37ff9892d09d6d86ac50e230549c7e53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb | 64 |
1 files changed, 61 insertions, 3 deletions
diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index d67b2176ab..dde0e9bb98 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -43,13 +43,71 @@ chip soc/intel/elkhartlake register "PcieClkSrcClkReq[4]" = "0x4" register "PcieClkSrcClkReq[5]" = "0x5" + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexI2C6] = PchSerialIoPci, + [PchSerialIoIndexI2C7] = PchSerialIoPci, + }" + + register "SerialIoI2cPadsTermination" = "{ + [PchSerialIoIndexI2C0] = 1, + [PchSerialIoIndexI2C1] = 1, + [PchSerialIoIndexI2C2] = 1, + [PchSerialIoIndexI2C3] = 1, + [PchSerialIoIndexI2C4] = 1, + [PchSerialIoIndexI2C5] = 1, + [PchSerialIoIndexI2C6] = 1, + [PchSerialIoIndexI2C7] = 1, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoHidden, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsEnable" = "{ + [PchSerialIoIndexGSPI0] = 1, + [PchSerialIoIndexGSPI1] = 1, + [PchSerialIoIndexGSPI2] = 1, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" + + register "SerialIoUartDmaEnable" = "{ + [PchSerialIoIndexUART0] = 1, + [PchSerialIoIndexUART1] = 1, + [PchSerialIoIndexUART2] = 1, + }" + # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 off end # SA Thermal device + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device device pci 08.0 off end # GNA device pci 09.0 off end # CPU Intel Trace Hub |