mb/intel/galileo: Drop support

As announced in the 4.20 release notes, support for the Intel Galileo
mainboard is moved to the 4.20 branch and dropped from master.

Change-Id: I132adf2782721738c954252665fdcd7bb8e1a1cd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>

16 files changed, 0 insertions, 879 deletions

diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig
deleted file mode 100644
index f22f1ee285..0000000000
--- a/src/mainboard/intel/galileo/Kconfig
+++ /dev/null
@@ -1,117 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-if BOARD_INTEL_GALILEO
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select BOARD_ROMSIZE_KB_8192
-	select ENABLE_BUILTIN_HSUART1
-	select HAVE_ACPI_TABLES
-	select SOC_INTEL_QUARK
-	select I2C_TPM
-	select TPM_ATMEL
-	select MAINBOARD_HAS_TPM2
-	select UDK_2017_BINDING
-
-
-config MAINBOARD_DIR
-	default "intel/galileo"
-
-config MAINBOARD_PART_NUMBER
-	default "Galileo"
-
-config GALILEO_GEN2
-	bool "Board generation: GEN1 (n) or GEN2 (y)"
-	default y
-	help
-	  The coreboot binary will configure only one generation of the Galileo
-	  board since coreboot can not determine the board generation at
-	  runtime.  Select which generation of the Galileo that coreboot
-	  should initialize.
-
-choice
-	prompt "FSP binary type"
-	default FSP_BUILD_TYPE_DEBUG
-
-config FSP_BUILD_TYPE_DEBUG
-	bool "Debug"
-	help
-	  Use the debug version of FSP
-config FSP_BUILD_TYPE_RELEASE
-	bool "Release"
-	help
-	  Use the release version of FSP
-
-endchoice
-
-config FSP_BUILD_TYPE
-	string
-	default "DEBUG" if FSP_BUILD_TYPE_DEBUG
-	default "RELEASE" if FSP_BUILD_TYPE_RELEASE
-
-choice
-	prompt "FSP type"
-	default FSP_TYPE_2_0_PEI
-
-config FSP_TYPE_2_0
-	bool "MemInit subroutine"
-	help
-	  FSP 2.0 implemented as subroutines, no EDK-II cores
-config FSP_TYPE_2_0_PEI
-	bool "SEC + PEI Core + MemInit PEIM"
-	help
-	  FSP 2.0 implemented using SEC and PEI core
-
-endchoice
-
-config FSP_TYPE
-	string
-	default "Fsp2_0" if FSP_TYPE_2_0
-	default "Fsp2_0Pei" if FSP_TYPE_2_0_PEI
-
-config FSP_DEBUG_ALL
-	bool "Enable all FSP debug support"
-	default y
-# Enable display and verification for coreboot build tests
-	select DISPLAY_HOBS
-	select DISPLAY_MTRRS
-	select DISPLAY_UPD_DATA
-	select DISPLAY_ESRAM_LAYOUT
-	select DISPLAY_FSP_CALLS_AND_STATUS
-	select DISPLAY_FSP_HEADER
-	select VERIFY_HOBS
-	help
-	  Turn on debug support to display HOBS, MTRRS, SMM_MEMORY_MAP, UPD_DATA
-	  also turn on FSP 2.0 debug support for ESRAM_LAYOUT,
-	  FSP_CALLS_AND_STATUS, FSP_HEADER, POSTCAR_CONSOLE and VERIFY_HOBS
-
-config VBOOT_WITH_CRYPTO_SHIELD
-	bool "Verified boot using the Crypto Shield board"
-	default n
-	select COLLECT_TIMESTAMPS
-	select VBOOT_SEPARATE_VERSTAGE
-	select VBOOT
-	select VBOOT_STARTS_IN_BOOTBLOCK
-	select VBOOT_VBNV_CMOS
-	help
-	  Perform a verified boot using the TPM on the Crypto Shield board.
-
-config DRIVER_TPM_I2C_ADDR
-	hex "Address of the I2C TPM chip"
-	depends on VBOOT_WITH_CRYPTO_SHIELD
-	default 0x29
-	help
-	  I2C address of the TPM chip on the Crypto Shield board.
-
-config FMDFILE
-	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot.fmd" if VBOOT
-
-config ENABLE_SD_TESTING
-	bool "Enable SD card testing"
-	default y
-	select COMMONLIB_STORAGE_SD
-	select SDHC_DEBUG
-	select STORAGE_LOG
-	select STORAGE_TEST
-
-endif # BOARD_INTEL_QUARK
diff --git a/src/mainboard/intel/galileo/Kconfig.name b/src/mainboard/intel/galileo/Kconfig.name
deleted file mode 100644
index 61ea9c3186..0000000000
--- a/src/mainboard/intel/galileo/Kconfig.name
+++ /dev/null
@@ -1,4 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-config BOARD_INTEL_GALILEO
-	bool "Galileo"
diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc
deleted file mode 100644
index 004f83280f..0000000000
--- a/src/mainboard/intel/galileo/Makefile.inc
+++ /dev/null
@@ -1,22 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/quark
-
-bootblock-y += gpio.c
-bootblock-y += reg_access.c
-
-verstage-y += gpio.c
-verstage-y += reg_access.c
-verstage-$(CONFIG_VBOOT) += vboot.c
-
-romstage-y += gpio.c
-romstage-y += reg_access.c
-romstage-$(CONFIG_COMMONLIB_STORAGE_SD) += sd.c
-romstage-$(CONFIG_VBOOT) += vboot.c
-
-postcar-y += gpio.c
-postcar-y += reg_access.c
-
-ramstage-y += gpio.c
-ramstage-y += reg_access.c
-ramstage-$(CONFIG_COMMONLIB_STORAGE_SD) += sd.c
diff --git a/src/mainboard/intel/galileo/board_info.txt b/src/mainboard/intel/galileo/board_info.txt
deleted file mode 100644
index 5af79f8de4..0000000000
--- a/src/mainboard/intel/galileo/board_info.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-Category: sbc
-ROM protocol: SPI
-Flashrom support: y
-Release year: 2014
diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb
deleted file mode 100644
index 4a806431ab..0000000000
--- a/src/mainboard/intel/galileo/devicetree.cb
+++ /dev/null
@@ -1,58 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-chip soc/intel/quark
-
-	############################################################
-	# Set the parameters for MemoryInit
-	############################################################
-
-	register "AddrMode" = "0"
-	register "ChanMask" = "1"		# Channel 0 enabled
-	register "ChanWidth" = "1"		# 16-bit channel
-	register "DramDensity" = "1"		# 1 Gib;
-	register "DramRonVal" = "0"		# 34 Ohm
-	register "DramRttNomVal" = "2"		# 120 Ohm
-	register "DramRttWrVal" = "0"		# off
-	register "DramSpeed" = "0"		# 800 MHz
-	register "DramType" = "0"		# DDR3
-	register "DramWidth" = "0"		# 8-bit
-	register "EccScrubBlkSize" = "2"	# 64 byte blocks
-	register "EccScrubInterval" = "0"	# ECC scrub disabled
-	register "Flags" = "MRC_FLAG_SCRAMBLE_EN"
-	register "FspReservedMemoryLength" = "0x00100000"	# Size in bytes
-	register "RankMask" = "1"		# RANK 0 enabled
-	register "SmmTsegSize" = "0"		# SMM Region size in MiB
-	register "SocRdOdtVal" = "0"		# off
-	register "SocWrRonVal" = "1"		# 32 Ohm
-	register "SocWrSlewRate" = "1"		# 4V/nSec
-	register "SrInt" = "3"			# 7.8 uSec
-	register "SrTemp" = "0"			# normal
-	register "tCL" = "6"			# clocks
-	register "tFAW" = "40000"		# picoseconds
-	register "tRAS" = "37500"		# picoseconds
-	register "tRRD" = "10000"		# picoseconds
-	register "tWTR" = "10000"		# picoseconds
-
-	############################################################
-	# Enable the devices
-	############################################################
-
-	device domain 0 on
-					# EDS Table 3
-		device pci 00.0 on end	# 8086 0958 - Host Bridge
-		device pci 14.0 on end	# 8086 08A7 - SD/SDIO/eMMC controller
-		device pci 14.1 off end	# 8086 0936 - HSUART 0
-		device pci 14.2 on end	# 8086 0939 - USB 2.0 Device port
-		device pci 14.3 on end	# 8086 0939 - USB EHCI Host controller
-		device pci 14.4 on end	# 8086 093A - USB OHCI Host controller
-		device pci 14.5 on end	# 8086 0936 - HSUART 1
-		device pci 14.6 off end	# 8086 0937 - 10/100 Ethernet MAC 0
-		device pci 14.7 off end	# 8086 0937 - 10/100 Ethernet MAC 1
-		device pci 15.0 on end	# 8086 0935 - SPI controller 0
-		device pci 15.1 on end	# 8086 0935 - SPI controller 1
-		device pci 15.2 on end	# 8086 0934 - I2C/GPIO controller
-		device pci 17.0 on end	# 8086 11C3 - PCIe Root Port 0
-		device pci 17.1 off end	# 8086 11C4 - PCIe Root Port 1
-		device pci 1f.0 on end	# 8086 095E - Legacy Bridge
-	end
-end
diff --git a/src/mainboard/intel/galileo/dsdt.asl b/src/mainboard/intel/galileo/dsdt.asl
deleted file mode 100644
index 11e3c7ea84..0000000000
--- a/src/mainboard/intel/galileo/dsdt.asl
+++ /dev/null
@@ -1,14 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <acpi/acpi.h>
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	ACPI_DSDT_REV_2,
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x20160220	// OEM revision
-)
-{
-	#include <acpi/dsdt_top.asl>
-}
diff --git a/src/mainboard/intel/galileo/gen1.h b/src/mainboard/intel/galileo/gen1.h
deleted file mode 100644
index 9c4cacbc83..0000000000
--- a/src/mainboard/intel/galileo/gen1.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* PCIe reset pin */
-#define GEN1_PCI_RESET_RESUMEWELL_GPIO		3
-
-/* Jumper J2 determines the slave address of Cypress I/O GPIO expander */
-#define GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO     5
-
-static const struct reg_script gen1_gpio_init[] = {
-	/* Initialize the legacy GPIO controller */
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGEN_CORE_WELL, 0x03),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGIO_CORE_WELL, 0x00),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGLVL_CORE_WELL, 0x00),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTPE_CORE_WELL, 0x00),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTNE_CORE_WELL, 0x00),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGGPE_CORE_WELL, 0x00),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGSMI_CORE_WELL, 0x00),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTS_CORE_WELL, 0x03),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_CNMIEN_CORE_WELL, 0x00),
-
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGEN_RESUME_WELL, 0x3f),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGIO_RESUME_WELL, 0x21),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGLVL_RESUME_WELL, 0x14),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTPE_RESUME_WELL, 0x00),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTNE_RESUME_WELL, 0x00),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGGPE_RESUME_WELL, 0x00),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGSMI_RESUME_WELL, 0x00),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTS_RESUME_WELL, 0x3f),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_RNMIEN_RESUME_WELL, 0x00),
-
-	/* Initialize the GPIO controller */
-	REG_GPIO_WRITE(GPIO_INTEN, 0),
-	REG_GPIO_WRITE(GPIO_INTSTATUS, 0),
-	REG_GPIO_WRITE(GPIO_SWPORTA_DR, 5),
-	REG_GPIO_WRITE(GPIO_SWPORTA_DDR, 0x15),
-	REG_GPIO_WRITE(GPIO_INTMASK, 0),
-	REG_GPIO_WRITE(GPIO_INTTYPE_LEVEL, 0),
-	REG_GPIO_WRITE(GPIO_INT_POLARITY, 0),
-	REG_GPIO_WRITE(GPIO_DEBOUNCE, 0),
-	REG_GPIO_WRITE(GPIO_LS_SYNC, 0),
-
-	/* Toggle the Cypress reset line */
-	REG_GPIO_OR(GPIO_SWPORTA_DR, BIT4),
-	REG_GPIO_AND(GPIO_SWPORTA_DR, ~BIT4),
-
-	REG_SCRIPT_END
-};
-
-static const struct reg_script gen1_hsuart0_0x20[] = {
-	/* Route UART0_TXD to LVL_TXD -> IO1 -> DIGITAL 1
-	 * Set IO1_MUX (EXP.PORT3_5) output, low
-	 * Set LVL_OE (GPIO_SUS2) output, high
-	 */
-
-	REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 3),
-	REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT5),
-	REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT3, ~BIT5),
-
-	/* Route DIGITAL 0 -> IO0 -> LVL_RXD -> UART0_RXD
-	 * Set IO0_MUX (EXP.PORT3_4) output, low
-	 * Set LVL_OE (GPIO_SUS2) output, high
-	 */
-	REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 3),
-	REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT4),
-	REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT3, ~BIT4),
-
-	REG_LEG_GPIO_OR(R_QNC_GPIO_RGEN_RESUME_WELL, BIT2),
-	REG_LEG_GPIO_AND(R_QNC_GPIO_RGIO_RESUME_WELL, ~BIT2),
-	REG_LEG_GPIO_OR(R_QNC_GPIO_RGLVL_RESUME_WELL, BIT2),
-
-	REG_SCRIPT_END
-};
-
-static const struct reg_script gen1_hsuart0_0x21[] = {
-	/* Route UART0_TXD to LVL_TXD -> IO1 -> DIGITAL 1
-	 * Set IO1_MUX (EXP.PORT3_5) output, low
-	 * Set LVL_OE (GPIO_SUS2) output, high
-	 */
-
-	REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 3),
-	REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT5),
-	REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT3, ~BIT5),
-
-	/* Route DIGITAL 0 -> IO0 -> LVL_RXD -> UART0_RXD
-	 * Set IO0_MUX (EXP.PORT3_4) output, low
-	 * Set LVL_OE (GPIO_SUS2) output, high
-	 */
-	REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 3),
-	REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT4),
-	REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT3, ~BIT4),
-
-	REG_LEG_GPIO_OR(R_QNC_GPIO_RGEN_RESUME_WELL, BIT2),
-	REG_LEG_GPIO_AND(R_QNC_GPIO_RGIO_RESUME_WELL, ~BIT2),
-	REG_LEG_GPIO_OR(R_QNC_GPIO_RGLVL_RESUME_WELL, BIT2),
-
-	REG_SCRIPT_END
-};
-
-static const struct reg_script gen1_i2c_0x20_init[] = {
-	/* Route I2C pins to Arduino header:
-	 * Clear I2C_MUX (GPORT1_BIT5) to route I2C to Arduino Shield connector
-	 *
-	 *	I2C_SDA -> ANALOG_A4
-	 *	I2C_SCL -> ANALOG_A5
-	 */
-	REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 1),
-	REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT5),
-	REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT1, ~BIT5),
-
-	/* Set all GPIO expander pins connected to the Reset Button as inputs
-	 * Configure RESET_N_SHLD (GPORT5_BIT0) and SW_RESET_N_SHLD
-	 * (GPORT5_BIT1) as inputs
-	 */
-	REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 5),
-	REG_I2C_OR(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, BIT1 | BIT0),
-
-	REG_SCRIPT_END
-};
-
-static const struct reg_script gen1_i2c_0x21_init[] = {
-	/* Route I2C pins to Arduino header:
-	 * Clear I2C_MUX (GPORT1_BIT5) to route I2C to Arduino Shield connector
-	 *
-	 *	I2C_SDA -> ANALOG_A4
-	 *	I2C_SCL -> ANALOG_A5
-	 */
-	REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 1),
-	REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT5),
-	REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT1, ~BIT5),
-
-	/* Set all GPIO expander pins connected to the Reset Button as inputs
-	 * Configure RESET_N_SHLD (GPORT5_BIT0) and SW_RESET_N_SHLD
-	 * (GPORT5_BIT1) as inputs
-	 */
-	REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 5),
-	REG_I2C_OR(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, BIT1 | BIT0),
-
-	REG_SCRIPT_END
-};
-
-static const struct reg_script gen1_tpm_reset_0x20[] = {
-	/* Reset the TPM using SW_RESET_N_SHLD (GPORT5_BIT1):
-	 * low, output, delay, input
-	 */
-	REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_OUTPUT5, ~BIT1),
-	REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_SELECT, 5),
-	REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, ~BIT1),
-	TIME_DELAY_USEC(5),
-	REG_I2C_OR(GEN1_I2C_GPIO_EXP_0x20, GEN1_GPIO_EXP_PORT_DIR, BIT1),
-
-	REG_SCRIPT_END
-};
-
-static const struct reg_script gen1_tpm_reset_0x21[] = {
-	/* Reset the TPM using SW_RESET_N_SHLD (GPORT5_BIT1):
-	 * low, output, delay, input
-	 */
-	REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_OUTPUT5, ~BIT1),
-	REG_I2C_WRITE(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_SELECT, 5),
-	REG_I2C_AND(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, ~BIT1),
-	TIME_DELAY_USEC(5),
-	REG_I2C_OR(GEN1_I2C_GPIO_EXP_0x21, GEN1_GPIO_EXP_PORT_DIR, BIT1),
-
-	REG_SCRIPT_END
-};
diff --git a/src/mainboard/intel/galileo/gen2.h b/src/mainboard/intel/galileo/gen2.h
deleted file mode 100644
index 141abd242b..0000000000
--- a/src/mainboard/intel/galileo/gen2.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-/* PCIe reset pin */
-#define GEN2_PCI_RESET_RESUMEWELL_GPIO		0
-
-static const struct reg_script gen2_gpio_init[] = {
-	/* Initialize the legacy GPIO controller */
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGEN_CORE_WELL, 0x03),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGIO_CORE_WELL, 0x03),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGLVL_CORE_WELL, 0x00),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTPE_CORE_WELL, 0x00),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTNE_CORE_WELL, 0x00),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGGPE_CORE_WELL, 0x00),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGSMI_CORE_WELL, 0x00),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_CGTS_CORE_WELL, 0x03),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_CNMIEN_CORE_WELL, 0x00),
-
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGEN_RESUME_WELL, 0x3f),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGIO_RESUME_WELL, 0x1c),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGLVL_RESUME_WELL, 0x02),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTPE_RESUME_WELL, 0x00),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTNE_RESUME_WELL, 0x00),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGGPE_RESUME_WELL, 0x00),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGSMI_RESUME_WELL, 0x00),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_RGTS_RESUME_WELL, 0x3f),
-	REG_LEG_GPIO_WRITE(R_QNC_GPIO_RNMIEN_RESUME_WELL, 0x00),
-
-	/* Initialize the GPIO controller */
-	REG_GPIO_WRITE(GPIO_INTEN, 0),
-	REG_GPIO_WRITE(GPIO_INTSTATUS, 0),
-	REG_GPIO_WRITE(GPIO_SWPORTA_DR, 5),
-	REG_GPIO_WRITE(GPIO_SWPORTA_DDR, 5),
-	REG_GPIO_WRITE(GPIO_INTMASK, 0),
-	REG_GPIO_WRITE(GPIO_INTTYPE_LEVEL, 0),
-	REG_GPIO_WRITE(GPIO_INT_POLARITY, 0),
-	REG_GPIO_WRITE(GPIO_DEBOUNCE, 0),
-	REG_GPIO_WRITE(GPIO_LS_SYNC, 0),
-
-	REG_SCRIPT_END
-};
-
-static const struct reg_script gen2_hsuart0[] = {
-	/* Route UART0_TXD to MUX7_Y -> BUF_IO1 -> IO1 -> DIGITAL 1
-	 * Set MUX7_SEL (EXP1.P1_5) high
-	 * Configure MUX7_SEL (EXP1.P1_5) as an output
-	 * Set LVL_B_OE6_N (EXP0.P1_4) low
-	 * Configure LVL_B_OE6_N (EXP0.P1_4) as an output
-	 */
-	REG_I2C_OR(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_OUTPUT1, BIT5),
-	REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG1, ~BIT5),
-	REG_I2C_AND(GEN2_I2C_GPIO_EXP0, GEN2_GPIO_EXP_OUTPUT1, ~BIT4),
-	REG_I2C_AND(GEN2_I2C_GPIO_EXP0, GEN2_GPIO_EXP_CONFIG1, ~BIT4),
-
-	/* Route DIGITAL 0 -> IO0 -> UART0_RXD
-	 * Set LVL_C_OE0_N (EXP1.P0_0) high
-	 * Configure LVL_C_OE0_N (EXP1.P0_0) as an output
-	 */
-	REG_I2C_OR(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_OUTPUT0, BIT0),
-	REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG0, ~BIT0),
-
-	REG_SCRIPT_END
-};
-
-static const struct reg_script gen2_i2c_init[] = {
-	/* Route I2C to Arduino Shield connector:
-	 * Set AMUX1_IN (EXP2.P1_4) low
-	 * Configure AMUX1_IN (EXP2.P1_4) as an output
-	 *
-	 *	I2C_SDA -> ANALOG_A4
-	 *	I2C_SCL -> ANALOG_A5
-	 */
-	REG_I2C_AND(GEN2_I2C_GPIO_EXP2, GEN2_GPIO_EXP_OUTPUT1, ~BIT4),
-	REG_I2C_AND(GEN2_I2C_GPIO_EXP2, GEN2_GPIO_EXP_CONFIG1, ~BIT4),
-
-	/* Set all GPIO expander pins connected to the Reset Button as inputs
-	 * Configure Reset Button(EXP1.P1_7) as an input
-	 * Disable pullup on Reset Button(EXP1.P1_7)
-	 * Configure Reset Button(EXP2.P1_7) as an input
-	 * Disable pullup on Reset Button(EXP2.P1_7)
-	 */
-	REG_I2C_OR(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG1, BIT7),
-	REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_PULL_UP_DOWN_EN1, ~BIT7),
-	REG_I2C_OR(GEN2_I2C_GPIO_EXP2, GEN2_GPIO_EXP_CONFIG1, BIT7),
-	REG_I2C_AND(GEN2_I2C_GPIO_EXP2, GEN2_GPIO_EXP_PULL_UP_DOWN_EN1, ~BIT7),
-
-	REG_SCRIPT_END
-};
-
-static const struct reg_script gen2_tpm_reset[] = {
-	/* Reset the TPM using SW_RESET_N_SHLD (EXP1 P1.7):
-	 * low, output, delay, input
-	 */
-	REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_OUTPUT1, ~BIT7),
-	REG_I2C_AND(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG1, ~BIT7),
-	TIME_DELAY_USEC(5),
-	REG_I2C_OR(GEN2_I2C_GPIO_EXP1, GEN2_GPIO_EXP_CONFIG1, BIT7),
-
-	REG_SCRIPT_END
-};
diff --git a/src/mainboard/intel/galileo/gpio.c b/src/mainboard/intel/galileo/gpio.c
deleted file mode 100644
index b145d6a1f0..0000000000
--- a/src/mainboard/intel/galileo/gpio.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <console/console.h>
-#include <soc/car.h>
-#include <soc/ramstage.h>
-#include "reg_access.h"
-#include "gen1.h"
-#include "gen2.h"
-
-void car_mainboard_pre_console_init(void)
-{
-	const struct reg_script *script;
-
-	/* Initialize the GPIO controllers */
-	if (CONFIG(GALILEO_GEN2))
-		script = gen2_gpio_init;
-	else
-		script = gen1_gpio_init;
-	reg_script_run(script);
-
-	/* Initialize the RXD and TXD paths for UART0 */
-	if (CONFIG(ENABLE_BUILTIN_HSUART0)) {
-		if (CONFIG(GALILEO_GEN2))
-			script = gen2_hsuart0;
-		else
-			script = (reg_legacy_gpio_read(
-				R_QNC_GPIO_RGLVL_RESUME_WELL)
-				& GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)
-				? gen1_hsuart0_0x20 : gen1_hsuart0_0x21;
-		reg_script_run(script);
-	}
-}
-
-void mainboard_gpio_i2c_init(struct device *dev)
-{
-	const struct reg_script *script;
-
-	printk(BIOS_INFO, "Galileo I2C chip initialization\n");
-
-	/* Determine the correct script for the board */
-	if (CONFIG(GALILEO_GEN2))
-		script = gen2_i2c_init;
-	else
-		/* Determine which I2C address is in use */
-		script = (reg_legacy_gpio_read(R_QNC_GPIO_RGLVL_RESUME_WELL)
-			& GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)
-			? gen1_i2c_0x20_init : gen1_i2c_0x21_init;
-
-	/* Initialize the I2C chips */
-	reg_script_run(script);
-}
-
-void mainboard_gpio_pcie_reset(uint32_t pin_value)
-{
-	uint32_t pin_number;
-	uint32_t value;
-
-	/* Determine the correct PCIe reset pin */
-	if (CONFIG(GALILEO_GEN2))
-		pin_number = GEN2_PCI_RESET_RESUMEWELL_GPIO;
-	else
-		pin_number = GEN1_PCI_RESET_RESUMEWELL_GPIO;
-
-	/* Update the PCIe reset value */
-	value = reg_legacy_gpio_read(R_QNC_GPIO_RGLVL_RESUME_WELL);
-	value = (value & ~(1 << pin_number)) | ((pin_value & 1) << pin_number);
-	reg_legacy_gpio_write(R_QNC_GPIO_RGLVL_RESUME_WELL, value);
-}
diff --git a/src/mainboard/intel/galileo/mainboard.c b/src/mainboard/intel/galileo/mainboard.c
deleted file mode 100644
index 2e3c3082f8..0000000000
--- a/src/mainboard/intel/galileo/mainboard.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <smbios.h>
-
-/* Set the board version */
-const char *smbios_mainboard_version(void)
-{
-	if (CONFIG(GALILEO_GEN2))
-		return "Gen 2";
-	return "1.0";
-}
diff --git a/src/mainboard/intel/galileo/reg_access.c b/src/mainboard/intel/galileo/reg_access.c
deleted file mode 100644
index c6d5240043..0000000000
--- a/src/mainboard/intel/galileo/reg_access.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#define __SIMPLE_DEVICE__
-
-#include <assert.h>
-#include <console/console.h>
-#include <device/i2c_simple.h>
-#include <soc/pci_devs.h>
-#include <soc/reg_access.h>
-#include "reg_access.h"
-
-static uint64_t reg_read(struct reg_script_context *ctx)
-{
-	int ret_code;
-	const struct reg_script *step;
-	uint8_t value = 0;
-
-	step = ctx->step;
-	switch (step->id) {
-	default:
-		printk(BIOS_ERR, "Unknown register set (0x%08x)!\n",
-			step->id);
-		ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING;
-		break;
-
-	case GEN1_I2C_GPIO_EXP_0x20:
-	case GEN1_I2C_GPIO_EXP_0x21:
-	case GEN2_I2C_GPIO_EXP0:
-	case GEN2_I2C_GPIO_EXP1:
-	case GEN2_I2C_GPIO_EXP2:
-	case GEN2_I2C_LED_PWM:
-		if (ctx->display_features)
-			printk(BIOS_INFO, "I2C chip 0x%02x: ", step->id);
-		ret_code = i2c_readb(0, step->id, (uint8_t)step->reg, &value);
-		ASSERT(ret_code == 2);
-		break;
-	}
-	return value;
-}
-
-static void reg_write(struct reg_script_context *ctx)
-{
-	int ret_code;
-	const struct reg_script *step;
-	uint8_t value;
-
-	step = ctx->step;
-	switch (step->id) {
-	default:
-		printk(BIOS_ERR, "Unknown register set (0x%08x)!\n",
-			step->id);
-		ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING;
-		break;
-
-	case GEN1_I2C_GPIO_EXP_0x20:
-	case GEN1_I2C_GPIO_EXP_0x21:
-	case GEN2_I2C_GPIO_EXP0:
-	case GEN2_I2C_GPIO_EXP1:
-	case GEN2_I2C_GPIO_EXP2:
-	case GEN2_I2C_LED_PWM:
-	case RMU_TEMP_REGS:
-		if (ctx->display_features)
-			printk(BIOS_INFO, "I2C chip 0x%02x: ", step->id);
-		value = (uint8_t)step->value;
-		ret_code = i2c_writeb(0, step->id, (uint8_t)step->reg, value);
-		ASSERT(ret_code == 2);
-		break;
-	}
-}
-
-const struct reg_script_bus_entry mainboard_reg_script_bus_table = {
-	MAINBOARD_TYPE, reg_read, reg_write
-};
-
-REG_SCRIPT_BUS_ENTRY(mainboard_reg_script_bus_table);
diff --git a/src/mainboard/intel/galileo/reg_access.h b/src/mainboard/intel/galileo/reg_access.h
deleted file mode 100644
index 23e420b228..0000000000
--- a/src/mainboard/intel/galileo/reg_access.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef _GALILEO_REG_ACCESS_H_
-#define _GALILEO_REG_ACCESS_H_
-
-#include <fsp/util.h>
-#include <reg_script.h>
-#include <soc/IntelQNCConfig.h>
-#include <soc/QuarkNcSocId.h>
-#include <soc/reg_access.h>
-
-enum {
-	MAINBOARD_TYPE = REG_SCRIPT_TYPE_MAINBOARD_BASE,
-	/* Add additional mainboard access types here*/
-};
-
-enum {
-	GEN1_I2C_GPIO_EXP_0x20 = 0x20,	/* Cypress CY8C9540A */
-	GEN1_I2C_GPIO_EXP_0x21 = 0x21,	/* Cypress CY8C9540A */
-
-	GEN2_I2C_GPIO_EXP0 = 0x25,	/* NXP PCAL9535A */
-	GEN2_I2C_GPIO_EXP1 = 0x26,	/* NXP PCAL9535A */
-	GEN2_I2C_GPIO_EXP2 = 0x27,	/* NXP PCAL9535A */
-	GEN2_I2C_LED_PWM = 0x47,	/* NXP PCAL9685 */
-};
-
-/* Cypress CY8C9548A registers */
-#define GEN1_GPIO_EXP_INPUT0		0x00
-#define GEN1_GPIO_EXP_INPUT1		0x01
-#define GEN1_GPIO_EXP_INPUT2		0x02
-#define GEN1_GPIO_EXP_INPUT3		0x03
-#define GEN1_GPIO_EXP_INPUT4		0x04
-#define GEN1_GPIO_EXP_INPUT5		0x05
-#define GEN1_GPIO_EXP_OUTPUT0		0x08
-#define GEN1_GPIO_EXP_OUTPUT1		0x09
-#define GEN1_GPIO_EXP_OUTPUT2		0x0a
-#define GEN1_GPIO_EXP_OUTPUT3		0x0b
-#define GEN1_GPIO_EXP_OUTPUT4		0x0c
-#define GEN1_GPIO_EXP_OUTPUT5		0x0d
-#define GEN1_GPIO_EXP_PORT_SELECT	0x18
-#define GEN1_GPIO_EXP_PORT_DIR		0x1c
-
-/* NXP PCAL9535A registers */
-#define GEN2_GPIO_EXP_INPUT0		0x00
-#define GEN2_GPIO_EXP_INPUT1		0x01
-#define GEN2_GPIO_EXP_OUTPUT0		0x02
-#define GEN2_GPIO_EXP_OUTPUT1		0x03
-#define GEN2_GPIO_EXP_POLARITY0		0x04
-#define GEN2_GPIO_EXP_POLARITY1		0x05
-#define GEN2_GPIO_EXP_CONFIG0		0x06
-#define GEN2_GPIO_EXP_CONFIG1		0x07
-#define GEN2_GPIO_EXP_INPUT_LATCH0	0x44
-#define GEN2_GPIO_EXP_INPUT_LATCH1	0x45
-#define GEN2_GPIO_EXP_PULL_UP_DOWN_EN0	0x46
-#define GEN2_GPIO_EXP_PULL_UP_DOWN_EN1	0x47
-#define GEN2_GPIO_EXP_PULL_UP_DOWN_SEL0	0x46
-#define GEN2_GPIO_EXP_PULL_UP_DOWN_SEL1	0x47
-
-#define MAINBOARD_ACCESS(cmd_, reg_, size_, mask_, value_, timeout_, reg_set_) \
-	_REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, MAINBOARD_TYPE,      \
-			       size_, reg_, mask_, value_, timeout_, reg_set_)
-
-/* I2C chip register access macros */
-#define REG_I2C_ACCESS(cmd_, reg_, mask_, value_, timeout_, slave_addr_) \
-	MAINBOARD_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_8, mask_, value_,   \
-		timeout_, slave_addr_)
-#define REG_I2C_READ(slave_addr_, reg_) \
-	REG_I2C_ACCESS(READ, reg_, 0, 0, 0, slave_addr_)
-#define REG_I2C_WRITE(slave_addr_, reg_, value_) \
-	REG_I2C_ACCESS(WRITE, reg_, 0, value_, 0, slave_addr_)
-#define REG_I2C_AND(slave_addr_, reg_, value_) \
-	REG_I2C_RMW(slave_addr_, reg_, value_, 0)
-#define REG_I2C_RMW(slave_addr_, reg_, mask_, value_) \
-	REG_I2C_ACCESS(RMW, reg_, mask_, value_, 0, slave_addr_)
-#define REG_I2C_RXW(slave_addr_, reg_, mask_, value_) \
-	REG_I2C_ACCESS(RXW, reg_, mask_, value_, 0, slave_addr_)
-#define REG_I2C_OR(slave_addr_, reg_, value_) \
-	REG_I2C_RMW(slave_addr_, reg_, 0xff, value_)
-#define REG_I2C_POLL(slave_addr_, reg_, mask_, value_, timeout_) \
-	REG_I2C_ACCESS(POLL, reg_, mask_, value_, timeout_, slave_addr_)
-#define REG_I2C_XOR(slave_addr_, reg_, value_) \
-	REG_I2C_RXW(slave_addr_, reg_, 0xff, value_)
-
-#endif /* _GALILEO_REG_ACCESS_H_ */
diff --git a/src/mainboard/intel/galileo/romstage.c b/src/mainboard/intel/galileo/romstage.c
deleted file mode 100644
index b65abd0501..0000000000
--- a/src/mainboard/intel/galileo/romstage.c
+++ /dev/null
@@ -1,5 +0,0 @@
-/* SPDX-License-Identifier: CC-PDDC */
-
-/* Please update the license if adding licensable material. */
-
-/* Dummy */
diff --git a/src/mainboard/intel/galileo/sd.c b/src/mainboard/intel/galileo/sd.c
deleted file mode 100644
index 65cd867d51..0000000000
--- a/src/mainboard/intel/galileo/sd.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <commonlib/sdhci.h>
-#include <commonlib/storage.h>
-
-void soc_sd_mmc_controller_quirks(struct sd_mmc_ctrlr *ctrlr)
-{
-	/* Specify the additional driver support */
-	ctrlr->caps |= DRVR_CAP_REMOVABLE;
-
-	/* ADMA currently not working on Quark */
-	ctrlr->caps &= ~DRVR_CAP_AUTO_CMD12;
-
-	/* Set initialization clock frequency */
-	ctrlr->f_min = 100 * CLOCK_KHZ;
-
-	/* Set the initialization delays */
-	ctrlr->mdelay_before_cmd0 = 1;
-	ctrlr->mdelay_after_cmd0 = 2;
-}
diff --git a/src/mainboard/intel/galileo/vboot.c b/src/mainboard/intel/galileo/vboot.c
deleted file mode 100644
index 4a7f424cd2..0000000000
--- a/src/mainboard/intel/galileo/vboot.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <bootmode.h>
-#include <device/i2c_simple.h>
-#include <soc/i2c.h>
-#include <soc/reg_access.h>
-#include <spi_flash.h>
-#include <security/vboot/vboot_common.h>
-#include <security/vboot/vbnv.h>
-
-#include "reg_access.h"
-#include "gen1.h"
-#include "gen2.h"
-
-int get_recovery_mode_switch(void)
-{
-	return 0;
-}
-
-int get_write_protect_state(void)
-{
-	/* Not write protected */
-	return 0;
-}
-
-void verstage_mainboard_init(void)
-{
-	const struct reg_script *script;
-
-	/* Crypto Shield I2C Addresses:
-	 *
-	 * 0x29: AT97S3204T - TPM 1.2
-	 * 0x50: ATAES132 - AES-128
-	 * 0x60: ATECC108 - Elliptical Curve
-	 * 0x64: ATSHA204 - SHA-256
-	 * 0x68: DS3231M - RTC
-	 */
-
-	/* Determine the correct script for the board */
-	if (CONFIG(GALILEO_GEN2))
-		script = gen2_i2c_init;
-	else
-		/* Determine which I2C address is in use */
-		script = (reg_legacy_gpio_read (R_QNC_GPIO_RGLVL_RESUME_WELL)
-			& GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)
-			? gen1_i2c_0x20_init : gen1_i2c_0x21_init;
-
-	/* Direct the I2C SDA and SCL signals to the Arduino connector */
-	reg_script_run(script);
-}
-
-void __weak vboot_platform_prepare_reboot(void)
-{
-	const struct reg_script *script;
-
-	/* Crypto Shield I2C Addresses:
-	 *
-	 * 0x29: AT97S3204T - TPM 1.2
-	 * 0x50: ATAES132 - AES-128
-	 * 0x60: ATECC108 - Elliptical Curve
-	 * 0x64: ATSHA204 - SHA-256
-	 * 0x68: DS3231M - RTC
-	 */
-
-	/* Determine the correct script for the board */
-	if (CONFIG(GALILEO_GEN2))
-		script = gen2_tpm_reset;
-	else
-		/* Determine which I2C address is in use */
-		script = (reg_legacy_gpio_read (R_QNC_GPIO_RGLVL_RESUME_WELL)
-			& GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)
-			? gen1_tpm_reset_0x20 : gen1_tpm_reset_0x21;
-
-	/* Reset the TPM */
-	reg_script_run(script);
-}
-
-int vbnv_cmos_failed(void)
-{
-	/* Indicate no failure until RTC failure bits are supported. */
-	return 0;
-}
diff --git a/src/mainboard/intel/galileo/vboot.fmd b/src/mainboard/intel/galileo/vboot.fmd
deleted file mode 100644
index 3a64387636..0000000000
--- a/src/mainboard/intel/galileo/vboot.fmd
+++ /dev/null
@@ -1,51 +0,0 @@
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but without any warranty; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-
-FLASH@0xff800000 0x800000 {
-	SI_ALL@0x0 0x200000 {
-		SI_DESC@0x0 0x1000
-		SI_ME@0x1000 0x1ff000
-	}
-	SI_BIOS@0x200000 0x600000 {
-		RW_SECTION_A@0x0 0xf0000 {
-			VBLOCK_A@0x0 0x10000
-			FW_MAIN_A(CBFS)@0x10000 0xdffc0
-			RW_FWID_A@0xeffc0 0x40
-		}
-		RW_SECTION_B@0xf0000 0xf0000 {
-			VBLOCK_B@0x0 0x10000
-			FW_MAIN_B(CBFS)@0x10000 0xdffc0
-			RW_FWID_B@0xeffc0 0x40
-		}
-		RW_MRC_CACHE@0x1e0000 0x10000
-		RW_ELOG(PRESERVE)@0x1f0000 0x4000
-		RW_SHARED@0x1f4000 0x4000 {
-			SHARED_DATA@0x0 0x2000
-			VBLOCK_DEV@0x2000 0x2000
-		}
-		RW_VPD(PRESERVE)@0x1f8000 0x2000
-		RW_NVRAM(PRESERVE)@0x1fa000 0x6000
-		SMMSTORE(PRESERVE)@0x200000 0x40000
-		RW_LEGACY(CBFS)@0x240000 0x1c0000
-		WP_RO@0x400000 0x200000 {
-			RO_VPD(PRESERVE)@0x0 0x4000
-			RO_UNUSED@0x4000 0xc000
-			RO_SECTION@0x10000 0x1f0000 {
-				FMAP@0x0 0x800
-				RO_FRID@0x800 0x40
-				RO_FRID_PAD@0x840 0x7c0
-				GBB@0x1000 0x7f000
-				COREBOOT(CBFS)@0x80000 0x170000
-			}
-		}
-	}
-}