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| author | Sean Rhodes <sean@starlabs.systems> | 2024-02-13 20:44:52 +0000 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-02-19 17:42:44 +0000 |
| commit | 00b81adfedd0f61beb3fd7f3775f5d215b6307c4 (patch) | |
| tree | f9399d44aab58601ffabae5d533cd20cedd5da37 /src/mainboard/intel | |
| parent | ccd18d1bb4a0d8a689c508833f2af21f92a4a8ac (diff) | |
soc/intel/alderlake: Include ADL-N ID 5 0x4618
This patch adds support for using ADL N 4-core MCH ID 0x4618.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3e4855ce93666c54ab35def9b58e4b13bc9a8672
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/adlrvp/ramstage.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/ramstage.c b/src/mainboard/intel/adlrvp/ramstage.c index 3ffc35be95..7a6bb5d04c 100644 --- a/src/mainboard/intel/adlrvp/ramstage.c +++ b/src/mainboard/intel/adlrvp/ramstage.c @@ -25,6 +25,7 @@ const struct cpu_power_limits limits[] = { { PCI_DID_INTEL_ADL_N_ID_2, 6, 3000, 6000, 25000, 25000, 78000 }, { PCI_DID_INTEL_ADL_N_ID_3, 6, 3000, 6000, 25000, 25000, 78000 }, { PCI_DID_INTEL_ADL_N_ID_4, 6, 3000, 6000, 25000, 25000, 78000 }, + { PCI_DID_INTEL_ADL_N_ID_5, 6, 3000, 6000, 25000, 25000, 78000 }, }; WEAK_DEV_PTR(dptf_policy); |