Drop Kconfig variable BOARD_HAS_HARD_RESET

hard_reset was indeed consolidated and moved into the southbridge
code a while ago, but the config variable was still kept alife, with
some duplicate code.

Change-Id: I60d4a87de916667f6e89353dfbe1a7b9eca380f7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1837
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

9 files changed, 12 insertions, 80 deletions

diff --git a/src/mainboard/intel/eagleheights/Kconfig b/src/mainboard/intel/eagleheights/Kconfig
index 4fd49fad10..0b765f920e 100644
--- a/src/mainboard/intel/eagleheights/Kconfig
+++ b/src/mainboard/intel/eagleheights/Kconfig
@@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SUPERIO_SMSC_SMSCSUPERIO
 	select HAVE_OPTION_TABLE
 	select HAVE_HARD_RESET
-	select BOARD_HAS_HARD_RESET
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select MMCONF_SUPPORT
diff --git a/src/mainboard/intel/eagleheights/reset.c b/src/mainboard/intel/eagleheights/reset.c
deleted file mode 100644
index 006c746dbb..0000000000
--- a/src/mainboard/intel/eagleheights/reset.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2008 coresystems GmbH
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- * MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include <reset.h>
-#if defined (__PRE_RAM__)
-#include <arch/romcc_io.h>
-#endif
-
-void soft_reset(void)
-{
-	outb(0x04, 0xcf9);
-}
-
-void hard_reset(void)
-{
-	outb(0x06, 0xcf9);
-}
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index 1e906efdcb..95ad59f9d4 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -33,7 +33,7 @@
 #include <cpu/intel/speedstep.h>
 #include "southbridge/intel/i3100/early_smbus.c"
 #include "southbridge/intel/i3100/early_lpc.c"
-#include "reset.c"
+#include "southbridge/intel/i3100/reset.c"
 #include "superio/intel/i3100/early_serial.c"
 #include "superio/smsc/smscsuperio/early_serial.c"
 #include "northbridge/intel/i3100/i3100.h"
diff --git a/src/mainboard/intel/jarrell/Kconfig b/src/mainboard/intel/jarrell/Kconfig
index a3c34f44b9..2a62777449 100644
--- a/src/mainboard/intel/jarrell/Kconfig
+++ b/src/mainboard/intel/jarrell/Kconfig
@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SOUTHBRIDGE_INTEL_I82801EX
 	select SUPERIO_NSC_PC87427
 	select ROMCC
-	select BOARD_HAS_HARD_RESET
 	select HAVE_OPTION_TABLE
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
diff --git a/src/mainboard/intel/jarrell/power_reset_check.c b/src/mainboard/intel/jarrell/power_reset_check.c
index 567d15c10f..0ac526f0ee 100644
--- a/src/mainboard/intel/jarrell/power_reset_check.c
+++ b/src/mainboard/intel/jarrell/power_reset_check.c
@@ -1,3 +1,13 @@
+void full_reset(void)
+{
+	/* Enable power on after power fail... */
+	unsigned byte;
+	byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
+	byte &= 0xfe;
+	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, byte);
+
+	outb(0x0e, 0xcf9);
+}
 
 static void power_down_reset_check(void)
 {
diff --git a/src/mainboard/intel/jarrell/reset.c b/src/mainboard/intel/jarrell/reset.c
deleted file mode 100644
index 2ecfa48b8f..0000000000
--- a/src/mainboard/intel/jarrell/reset.c
+++ /dev/null
@@ -1,31 +0,0 @@
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <reset.h>
-
-void soft_reset(void)
-{
-        outb(0x04, 0xcf9);
-}
-
-void hard_reset(void)
-{
-        outb(0x02, 0xcf9);
-        outb(0x06, 0xcf9);
-}
-
-#ifndef __ROMCC__
-/* Used only board-internally by power_reset_check.c and jarell_fixups.c */
-void full_reset(void);
-#endif
-
-void full_reset(void)
-{
-	/* Enable power on after power fail... */
-	unsigned byte;
-	byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4);
-	byte &= 0xfe;
-	pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, byte);
-
-        outb(0x0e, 0xcf9);
-}
-
diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c
index 3eff025968..784e7df3e6 100644
--- a/src/mainboard/intel/jarrell/romstage.c
+++ b/src/mainboard/intel/jarrell/romstage.c
@@ -12,7 +12,7 @@
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "cpu/x86/mtrr/earlymtrr.c"
 #include "watchdog.c"
-#include "reset.c"
+#include "southbridge/intel/i82801ex/reset.c"
 #include "power_reset_check.c"
 #include "jarrell_fixups.c"
 #include "superio/nsc/pc87427/early_init.c"
diff --git a/src/mainboard/intel/xe7501devkit/Kconfig b/src/mainboard/intel/xe7501devkit/Kconfig
index 3f314a623b..276b1f7b5b 100644
--- a/src/mainboard/intel/xe7501devkit/Kconfig
+++ b/src/mainboard/intel/xe7501devkit/Kconfig
@@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select SOUTHBRIDGE_INTEL_I82801CX
 	select SUPERIO_SMSC_LPC47B272
 	select ROMCC
-	select BOARD_HAS_HARD_RESET
 	select HAVE_PIRQ_TABLE
 	select HAVE_MP_TABLE
 	select UDELAY_TSC
diff --git a/src/mainboard/intel/xe7501devkit/reset.c b/src/mainboard/intel/xe7501devkit/reset.c
deleted file mode 100644
index 106920acbe..0000000000
--- a/src/mainboard/intel/xe7501devkit/reset.c
+++ /dev/null
@@ -1,8 +0,0 @@
-#include <reset.h>
-
-#include "southbridge/intel/i82801cx/i82801cx.h"
-
-void hard_reset(void)
-{
-	i82801cx_hard_reset();
-}