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authorMarshall Dawson <marshalldawson3rd@gmail.com>2018-09-10 13:28:49 -0600
committerMarshall Dawson <marshalldawson3rd@gmail.com>2018-09-11 20:36:11 +0000
commitf0de242df0a1b83e01dfa3898e561dca1f4f2ef3 (patch)
tree26f005d7bc26b534d4e7cf5b377378ab80462b3f /src/mainboard/intel
parent63ebb5bde1572e49dfa1c9ef627e486cd01b8163 (diff)
amd/stoneyridge: Set BERT region size when no TSEG used
Expand the BERT reserved region size setting to account for the possibility of no TSEG configuration. This change is only for completeness, as stoneyridge must always use TSEG. Change-Id: I90753fa408cfac4de38aff08979c45349bb62a66 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28554 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Diffstat (limited to 'src/mainboard/intel')
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