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authorStefan Reinauer <stepan@openbios.org>2005-12-03 23:48:17 +0000
committerStefan Reinauer <stepan@openbios.org>2005-12-03 23:48:17 +0000
commitbbbfd9d1906cb2d99385eae845a13a311f77ef78 (patch)
tree0485f8ebc4bdd026e0e43bdaa36a0ac0c4fd5c6a /src/mainboard/intel
parentbd25fe979bee6a2912b671b7f811192c51c5f95f (diff)
smaller fixups here and there, allowing some motherboards to compile or
to fail later than before. dos2unix'ed the xe7501devkit files, that might have caused some problems before. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/xe7501devkit/Config.lb440
-rw-r--r--src/mainboard/intel/xe7501devkit/Options.lb473
-rw-r--r--src/mainboard/intel/xe7501devkit/acpi_tables.c242
-rw-r--r--src/mainboard/intel/xe7501devkit/auto.c184
-rw-r--r--src/mainboard/intel/xe7501devkit/bus.h34
-rw-r--r--src/mainboard/intel/xe7501devkit/chip.h12
-rw-r--r--src/mainboard/intel/xe7501devkit/cmos.layout4
-rw-r--r--src/mainboard/intel/xe7501devkit/failover.c94
-rw-r--r--src/mainboard/intel/xe7501devkit/ioapic.h22
-rw-r--r--src/mainboard/intel/xe7501devkit/irq_tables.c148
-rw-r--r--src/mainboard/intel/xe7501devkit/mainboard.c24
-rw-r--r--src/mainboard/intel/xe7501devkit/mptable.c360
12 files changed, 1024 insertions, 1013 deletions
diff --git a/src/mainboard/intel/xe7501devkit/Config.lb b/src/mainboard/intel/xe7501devkit/Config.lb
index 65ea45b566..2e1986369e 100644
--- a/src/mainboard/intel/xe7501devkit/Config.lb
+++ b/src/mainboard/intel/xe7501devkit/Config.lb
@@ -1,224 +1,224 @@
-##################################################################
-## BEGIN BOILERPLATE - DO NOT EDIT
-##
-## Compute the location and size of where this firmware image
-## (linuxBIOS plus payload) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
-# The fallback image uses FALLBACK_SIZE bytes at the end of the ROM
-
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-
-else
-# The normal image goes at the beginning of the LinuxBIOS ROM region
-# and uses all the remaining space
-
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute where this copy of linuxBIOS will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-default XIP_ROM_SIZE = 65536
-default XIP_ROM_BASE = ((( _ROMBASE + ROM_IMAGE_SIZE ) / XIP_ROM_SIZE ) * XIP_ROM_SIZE - XIP_ROM_SIZE )
-
-## END BOILERPLATE
-##################################################################
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
-if HAVE_ACPI_TABLES object acpi_tables.o end
-object reset.o
-
-# Include the VGA option ROM, but only if we're compiled to use it
-if CONFIG_PCI_ROM_RUN
- if CONFIG_CONSOLE_VGA
- object vgarom.S
- else
- object no_vgarom.S
- end
-else
- object no_vgarom.S
-end
-
-##
-## Romcc output
-##
-makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ./romcc"
- action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ./romcc"
- action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
- action "./romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
- action "./romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit linuxBIOS entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where linuxBIOS is entered)
-##
-if HAVE_FALLBACK_BOOT
- if USE_FALLBACK_IMAGE
- mainboardinit cpu/x86/16bit/reset16.inc
- ldscript /cpu/x86/16bit/reset16.lds
- else
- mainboardinit cpu/x86/32bit/reset32.inc
- ldscript /cpu/x86/32bit/reset32.lds
- end
-else
- mainboardinit cpu/x86/16bit/reset16.inc
- ldscript /cpu/x86/16bit/reset16.lds
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of linuxBIOS startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-##
-## Include the secondary Configuration files
-##
-dir /pc80
-
-if CONFIG_CHIP_NAME
- config chip.h
-end
-
-# based on sample config for tyan/s2735
-chip northbridge/intel/e7501
- device pci_domain 0 on
- device pci 0.0 on end # Chipset host controller
- device pci 0.1 on end # Host RASUM controller
- device pci 2.0 on # Hub interface B
- chip southbridge/intel/i82870 # P64H2
- device pci 1c.0 on end # IOAPIC - bus B
- device pci 1d.0 on end # Hub to PCI-B bridge
- device pci 1e.0 on end # IOAPIC - bus A
- device pci 1f.0 on end # Hub to PCI-A bridge
- end
- end
- device pci 3.0 off end # Hub interface C (82808AA connector - disable for now)
- device pci 4.0 on # Hub interface D
- chip southbridge/intel/i82870 # P64H2
- device pci 1c.0 on end # IOAPIC - bus B
- device pci 1d.0 on end # Hub to PCI-B bridge
- device pci 1e.0 on end # IOAPIC - bus A
- device pci 1f.0 on end # Hub to PCI-A bridge
- end
- end
- device pci 6.0 on end # E7501 Power management registers? (undocumented)
- chip southbridge/intel/i82801ca
- device pci 1d.0 off end # USB (might not work, Southbridge code needs looking at)
- device pci 1d.1 off end # USB (not populated)
- device pci 1d.2 off end # USB (not populated)
- device pci 1e.0 on # Hub to PCI bridge
+##################################################################
+## BEGIN BOILERPLATE - DO NOT EDIT
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus payload) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+# The fallback image uses FALLBACK_SIZE bytes at the end of the ROM
+
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+
+else
+# The normal image goes at the beginning of the LinuxBIOS ROM region
+# and uses all the remaining space
+
+ default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
+ default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+default XIP_ROM_SIZE = 65536
+default XIP_ROM_BASE = ((( _ROMBASE + ROM_IMAGE_SIZE ) / XIP_ROM_SIZE ) * XIP_ROM_SIZE - XIP_ROM_SIZE )
+
+## END BOILERPLATE
+##################################################################
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+if HAVE_MP_TABLE object mptable.o end
+if HAVE_PIRQ_TABLE object irq_tables.o end
+if HAVE_ACPI_TABLES object acpi_tables.o end
+object reset.o
+
+# Include the VGA option ROM, but only if we're compiled to use it
+if CONFIG_PCI_ROM_RUN
+ if CONFIG_CONSOLE_VGA
+ object vgarom.S
+ else
+ object no_vgarom.S
+ end
+else
+ object no_vgarom.S
+end
+
+##
+## Romcc output
+##
+makerule ./failover.E
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./failover.inc
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./auto.E
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if HAVE_FALLBACK_BOOT
+ if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+ else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+ end
+else
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+end
+
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+###
+### This is the early phase of linuxBIOS startup
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if USE_FALLBACK_IMAGE
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+##
+## Include the secondary Configuration files
+##
+dir /pc80
+
+if CONFIG_CHIP_NAME
+ config chip.h
+end
+
+# based on sample config for tyan/s2735
+chip northbridge/intel/e7501
+ device pci_domain 0 on
+ device pci 0.0 on end # Chipset host controller
+ device pci 0.1 on end # Host RASUM controller
+ device pci 2.0 on # Hub interface B
+ chip southbridge/intel/i82870 # P64H2
+ device pci 1c.0 on end # IOAPIC - bus B
+ device pci 1d.0 on end # Hub to PCI-B bridge
+ device pci 1e.0 on end # IOAPIC - bus A
+ device pci 1f.0 on end # Hub to PCI-A bridge
+ end
+ end
+ device pci 3.0 off end # Hub interface C (82808AA connector - disable for now)
+ device pci 4.0 on # Hub interface D
+ chip southbridge/intel/i82870 # P64H2
+ device pci 1c.0 on end # IOAPIC - bus B
+ device pci 1d.0 on end # Hub to PCI-B bridge
+ device pci 1e.0 on end # IOAPIC - bus A
+ device pci 1f.0 on end # Hub to PCI-A bridge
+ end
+ end
+ device pci 6.0 on end # E7501 Power management registers? (undocumented)
+ chip southbridge/intel/i82801ca
+ device pci 1d.0 off end # USB (might not work, Southbridge code needs looking at)
+ device pci 1d.1 off end # USB (not populated)
+ device pci 1d.2 off end # USB (not populated)
+ device pci 1e.0 on # Hub to PCI bridge
chip drivers/pci/onboard # VGA ROM
device pci 0.0 on end
register "rom_address" = "_vgarom_start"
- end
+ end
end
- device pci 1f.0 on # LPC bridge
- chip superio/smsc/lpc47b272
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.3 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.4 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.5 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.7 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1 # Keyboard interrupt
- irq 0x72 = 12 # Mouse interrupt
- end
- device pnp 2e.a off end # ACPI
- end
- end
- device pci 1f.1 on end # IDE
- device pci 1f.3 on end # SMBus
- device pci 1f.5 off end # AC97 Audio
- device pci 1f.6 off end # AC97 Modem
- end # SB
- end # PCI_DOMAIN
- device apic_cluster 0 on
- chip cpu/intel/socket_mPGA604_533Mhz
- device apic 0 on end
- end
- chip cpu/intel/socket_mPGA604_533Mhz
- device apic 6 on end
- end
- end
-end
+ device pci 1f.0 on # LPC bridge
+ chip superio/smsc/lpc47b272
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.3 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.4 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.5 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.7 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # Keyboard interrupt
+ irq 0x72 = 12 # Mouse interrupt
+ end
+ device pnp 2e.a off end # ACPI
+ end
+ end
+ device pci 1f.1 on end # IDE
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # AC97 Audio
+ device pci 1f.6 off end # AC97 Modem
+ end # SB
+ end # PCI_DOMAIN
+ device apic_cluster 0 on
+ chip cpu/intel/socket_mPGA604_533Mhz
+ device apic 0 on end
+ end
+ chip cpu/intel/socket_mPGA604_533Mhz
+ device apic 6 on end
+ end
+ end
+end
diff --git a/src/mainboard/intel/xe7501devkit/Options.lb b/src/mainboard/intel/xe7501devkit/Options.lb
index b034ed6158..0b0588b2e6 100644
--- a/src/mainboard/intel/xe7501devkit/Options.lb
+++ b/src/mainboard/intel/xe7501devkit/Options.lb
@@ -1,234 +1,239 @@
-uses HAVE_MP_TABLE
-uses HAVE_ACPI_TABLES
-uses HAVE_PIRQ_TABLE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_OPTION_TABLE
-uses IRQ_SLOT_COUNT
-uses CONFIG_MAX_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses CONFIG_ROM_STREAM
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses OBJCOPY
-uses CONFIG_CHIP_NAME
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses DEBUG
-uses CPU_OPT
-uses CONFIG_IDE
-
-## The default definitions are used for these
-uses CONFIG_ROM_STREAM_START
-uses PAYLOAD_SIZE
-
-## These are defined in target Config.lb, don't add here
-uses USE_FALLBACK_IMAGE
-uses ROM_SIZE
-uses ROM_IMAGE_SIZE
-uses FALLBACK_SIZE
-uses LINUXBIOS_EXTRA_VERSION
-
-## These are defined in mainboard Config.lb, don't add here
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot?
-##
-default HAVE_FALLBACK_BOOT=0
-
-
-## Delay timer options
-##
-default CONFIG_UDELAY_TSC=1
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=12
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default HAVE_MP_TABLE=1
-
-## Build code to export ACPI tables?
-default HAVE_ACPI_TABLES=1
-
-##
-## Build code to export a CMOS option table?
-##
-default HAVE_OPTION_TABLE=0
-
-## CMOS checksum definitions (units == bytes)
-## These must match the checksum record in cmos.layout
-default LB_CKS_RANGE_START=128
-default LB_CKS_RANGE_END=130
-default LB_CKS_LOC=131
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-## NOTE: CONFIG_MAX_CPUS is the number of LOGICAL CPUs,
-## so if CONFIG_LOGICAL_CPUS is 1, CONFIG_MAX_CPUS should be 4.
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-default CONFIG_LOGICAL_CPUS=0
-default CONFIG_MAX_PHYSICAL_CPUS=2
-
-# VGA Console
-# NOTE: to initialize VGA, need to copy the VGA option ROM from the factory BIOS
-# to VGA.rom
-default CONFIG_CONSOLE_VGA=0
-default CONFIG_PCI_ROM_RUN=0
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Motherboard identification
-##
-default MAINBOARD_PART_NUMBER="EIDXE7501DEVKIT"
-default MAINBOARD_VENDOR="Intel"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480
-
-###
-### LinuxBIOS layout values
-###
-
-##
-## Use a small 8K stack
-##
-default STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default HEAP_SIZE=0x4000
-
-##
-## CMOS settings not currently supported due to conflicts with factory BIOS
-##
-default USE_OPTION_TABLE = 0
-
-##
-## LinuxBIOS C code runs at this location in RAM
-##
-default _RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_STREAM = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
-
-# Select the serial console base port
-default TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
-
-##
-### Select the linuxBIOS loglevel
-##
-## EMERG 1 system is unusable
-## ALERT 2 action must be taken immediately
-## CRIT 3 critical conditions
-## ERR 4 error conditions
-## WARNING 5 warning conditions
-## NOTICE 6 normal but significant condition
-## INFO 7 informational
-## DEBUG 8 debug-level messages
-## SPEW 9 Way too many details
-
-## Request this level of debugging output
-default DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-## Things we may not have
-default CONFIG_IDE=1
-
-default DEBUG=1
-default CPU_OPT="-g"
-default CONFIG_CHIP_NAME=1
-
-### End Options.lb
-end
+uses HAVE_MP_TABLE
+uses HAVE_ACPI_TABLES
+uses HAVE_PIRQ_TABLE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_OPTION_TABLE
+uses IRQ_SLOT_COUNT
+uses CONFIG_MAX_CPUS
+uses CONFIG_LOGICAL_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
+uses CONFIG_IOAPIC
+uses CONFIG_SMP
+uses CONFIG_ROM_STREAM
+uses STACK_SIZE
+uses HEAP_SIZE
+uses USE_OPTION_TABLE
+uses LB_CKS_RANGE_START
+uses LB_CKS_RANGE_END
+uses LB_CKS_LOC
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses MAINBOARD
+uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses _RAMBASE
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_CONSOLE_SERIAL8250
+uses CONFIG_UDELAY_TSC
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+uses HAVE_INIT_TIMER
+uses CONFIG_GDB_STUB
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses CONFIG_CHIP_NAME
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_PCI_ROM_RUN
+uses DEBUG
+uses CPU_OPT
+uses CONFIG_IDE
+
+## The default definitions are used for these
+uses CONFIG_ROM_STREAM_START
+uses PAYLOAD_SIZE
+
+## These are defined in target Config.lb, don't add here
+uses USE_FALLBACK_IMAGE
+uses ROM_SIZE
+uses ROM_IMAGE_SIZE
+uses FALLBACK_SIZE
+uses LINUXBIOS_EXTRA_VERSION
+
+## These are defined in mainboard Config.lb, don't add here
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses _ROMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+
+###
+### Build options
+###
+
+##
+## ROM_SIZE is the size of boot ROM that this board will use.
+##
+default ROM_SIZE=2097152
+
+##
+## Build code for the fallback boot?
+##
+default HAVE_FALLBACK_BOOT=0
+
+
+## Delay timer options
+##
+default CONFIG_UDELAY_TSC=1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=12
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default HAVE_MP_TABLE=1
+
+## Build code to export ACPI tables?
+default HAVE_ACPI_TABLES=1
+
+##
+## Build code to export a CMOS option table?
+##
+default HAVE_OPTION_TABLE=0
+
+## CMOS checksum definitions (units == bytes)
+## These must match the checksum record in cmos.layout
+default LB_CKS_RANGE_START=128
+default LB_CKS_RANGE_END=130
+default LB_CKS_LOC=131
+
+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+## NOTE: CONFIG_MAX_CPUS is the number of LOGICAL CPUs,
+## so if CONFIG_LOGICAL_CPUS is 1, CONFIG_MAX_CPUS should be 4.
+##
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=2
+default CONFIG_LOGICAL_CPUS=0
+default CONFIG_MAX_PHYSICAL_CPUS=2
+
+# VGA Console
+# NOTE: to initialize VGA, need to copy the VGA option ROM from the factory BIOS
+# to VGA.rom
+default CONFIG_CONSOLE_VGA=0
+default CONFIG_PCI_ROM_RUN=0
+
+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_IOAPIC=1
+
+##
+## Motherboard identification
+##
+default MAINBOARD_PART_NUMBER="EIDXE7501DEVKIT"
+default MAINBOARD_VENDOR="Intel"
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086
+default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480
+
+###
+### LinuxBIOS layout values
+###
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x2000
+
+##
+## Use a small 16K heap
+##
+default HEAP_SIZE=0x4000
+
+##
+## CMOS settings not currently supported due to conflicts with factory BIOS
+##
+default USE_OPTION_TABLE = 0
+
+##
+## LinuxBIOS C code runs at this location in RAM
+##
+default _RAMBASE=0x00004000
+
+##
+## Load the payload from the ROM
+##
+default CONFIG_ROM_STREAM = 1
+
+###
+### Defaults of options that you may want to override in the target config file
+###
+
+##
+## The default compiler
+##
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## Disable the gdb stub by default
+##
+default CONFIG_GDB_STUB=0
+
+##
+## The Serial Console
+##
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default TTYS0_BAUD=115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200
+
+# Select the serial console base port
+default TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS=0x3
+
+##
+### Select the linuxBIOS loglevel
+##
+## EMERG 1 system is unusable
+## ALERT 2 action must be taken immediately
+## CRIT 3 critical conditions
+## ERR 4 error conditions
+## WARNING 5 warning conditions
+## NOTICE 6 normal but significant condition
+## INFO 7 informational
+## DEBUG 8 debug-level messages
+## SPEW 9 Way too many details
+
+## Request this level of debugging output
+default DEFAULT_CONSOLE_LOGLEVEL=8
+## At a maximum only compile in this level of debugging
+default MAXIMUM_CONSOLE_LOGLEVEL=8
+
+##
+## Select power on after power fail setting
+default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+
+## Things we may not have
+default CONFIG_IDE=1
+
+default DEBUG=1
+default CPU_OPT="-g"
+default CONFIG_CHIP_NAME=1
+
+### End Options.lb
+end
diff --git a/src/mainboard/intel/xe7501devkit/acpi_tables.c b/src/mainboard/intel/xe7501devkit/acpi_tables.c
index 94cdb871ef..7d1261c57f 100644
--- a/src/mainboard/intel/xe7501devkit/acpi_tables.c
+++ b/src/mainboard/intel/xe7501devkit/acpi_tables.c
@@ -1,118 +1,124 @@
-/*
- * Ported to Intel XE7501DEVKIT from Island Aruma
- * written by Stefan Reinauer <stepan@openbios.org>
- * (C) 2005 Stefan Reinauer
- * (C) 2005 Digital Design Corporation
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <assert.h>
-#include "bus.h"
-#include "ioapic.h"
-
-unsigned long acpi_dump_apics(unsigned long current)
-{
- unsigned int irq_start = 0;
- device_t dev = 0;
- struct resource* res = NULL;
-
-
- // SJM: Hard-code CPU LAPIC entries for now
- // Use SourcePoint numbering of processors
- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 6);
- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 7);
- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 0);
- current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 1);
-
-
- // Southbridge IOAPIC
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH3, 0xfec00000, irq_start);
- irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
-
- // P64H2#2 Bus A IOAPIC
- dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
- if (!dev)
- BUG(); // Config.lb error?
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_2_BUS_A, res->base, irq_start);
- irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
-
- // P64H2#2 Bus B IOAPIC
- dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
- if (!dev)
- BUG(); // Config.lb error?
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_2_BUS_B, res->base, irq_start);
- irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
-
-
- // P64H2#1 Bus A IOAPIC
- dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));
- if (!dev)
- BUG(); // Config.lb error?
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_1_BUS_A, res->base, irq_start);
- irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
-
- // P64H2#1 Bus B IOAPIC
- dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));
- if (!dev)
- BUG(); // Config.lb error?
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_1_BUS_B, res->base, irq_start);
- irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
-
- // Map ISA IRQ 0 to IRQ 2
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0);
-
- // IRQ9 differs from ISA standard - ours is active high, level-triggered
- current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xD);
-
- return current;
-}
-
-
-unsigned long write_acpi_tables(unsigned long start)
-{
- unsigned long current;
- acpi_rsdp_t *rsdp;
- acpi_rsdt_t *rsdt;
- acpi_madt_t *madt;
-
- /* Align ACPI tables to 16byte */
- start = ( start + 0x0f ) & -0x10;
- current = start;
-
- printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
-
- /* We need at least an RSDP and an RSDT Table */
- rsdp = (acpi_rsdp_t *) current;
- current += sizeof(acpi_rsdp_t);
- rsdt = (acpi_rsdt_t *) current;
- current += sizeof(acpi_rsdt_t);
-
- /* clear all table memory */
- memset((void *)start, 0, current - start);
-
- acpi_write_rsdp(rsdp, rsdt);
- acpi_write_rsdt(rsdt);
-
- /*
- * We explicitly add these tables later on:
- */
- /* QNX wants an MADT */
- printk_debug("ACPI: * MADT\n");
-
- madt = (acpi_madt_t *) current;
- acpi_create_madt(madt);
- current+=madt->header.length;
- acpi_add_table(rsdt,madt);
-
- printk_info("ACPI: done.\n");
- return current;
-}
-
+/*
+ * Ported to Intel XE7501DEVKIT from Agami Aruma
+ * written by Stefan Reinauer <stepan@openbios.org>
+ * (C) 2005 Stefan Reinauer
+ * (C) 2005 Digital Design Corporation
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <assert.h>
+#include "bus.h"
+#include "ioapic.h"
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ // Not implemented
+ return 0;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ unsigned int irq_start = 0;
+ device_t dev = 0;
+ struct resource* res = NULL;
+
+
+ // SJM: Hard-code CPU LAPIC entries for now
+ // Use SourcePoint numbering of processors
+ current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 6);
+ current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 7);
+ current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 0);
+ current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 1);
+
+
+ // Southbridge IOAPIC
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH3, 0xfec00000, irq_start);
+ irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
+
+ // P64H2#2 Bus A IOAPIC
+ dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
+ if (!dev)
+ BUG(); // Config.lb error?
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_2_BUS_A, res->base, irq_start);
+ irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
+
+ // P64H2#2 Bus B IOAPIC
+ dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
+ if (!dev)
+ BUG(); // Config.lb error?
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_2_BUS_B, res->base, irq_start);
+ irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
+
+
+ // P64H2#1 Bus A IOAPIC
+ dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));
+ if (!dev)
+ BUG(); // Config.lb error?
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_1_BUS_A, res->base, irq_start);
+ irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
+
+ // P64H2#1 Bus B IOAPIC
+ dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));
+ if (!dev)
+ BUG(); // Config.lb error?
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_1_BUS_B, res->base, irq_start);
+ irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
+
+ // Map ISA IRQ 0 to IRQ 2
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0);
+
+ // IRQ9 differs from ISA standard - ours is active high, level-triggered
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xD);
+
+ return current;
+}
+
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_madt_t *madt;
+
+ /* Align ACPI tables to 16byte */
+ start = ( start + 0x0f ) & -0x10;
+ current = start;
+
+ printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+
+ /* clear all table memory */
+ memset((void *)start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt);
+ acpi_write_rsdt(rsdt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ /* QNX wants an MADT */
+ printk_debug("ACPI: * MADT\n");
+
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current+=madt->header.length;
+ acpi_add_table(rsdt,madt);
+
+ printk_info("ACPI: done.\n");
+ return current;
+}
+
diff --git a/src/mainboard/intel/xe7501devkit/auto.c b/src/mainboard/intel/xe7501devkit/auto.c
index 8c635720af..1bd83a3187 100644
--- a/src/mainboard/intel/xe7501devkit/auto.c
+++ b/src/mainboard/intel/xe7501devkit/auto.c
@@ -1,92 +1,92 @@
-#define ASSEMBLY 1
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "southbridge/intel/i82801ca/i82801ca_early_smbus.c"
-#include "northbridge/intel/e7501/raminit.h"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/e7501/debug.c"
-#include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "cpu/x86/bist.h"
-
-#define SUPERIO_PORT 0x2e
-#define SERIAL_DEV PNP_DEV(SUPERIO_PORT, LPC47B272_SP1)
-
-static void hard_reset(void)
-{
- outb(0x0e, 0x0cf9);
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/intel/e7501/raminit.c"
-#include "northbridge/intel/e7501/reset_test.c"
-#include "sdram/generic_sdram.c"
-
-
-// This function MUST appear last (ROMCC limitation)
-static void main(unsigned long bist)
-{
- static const struct mem_controller memctrl[] = {
- {
- .d0 = PCI_DEV(0, 0, 0),
- .d0f1 = PCI_DEV(0, 0, 1),
- .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
- .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
- },
- };
-
- if (bist == 0)
- {
- // Skip this if there was a built in self test failure
-
- early_mtrr_init();
- enable_lapic();
- }
-
- // Get the serial port running and print a welcome banner
-
- lpc47b272_enable_serial(SERIAL_DEV, TTYS0_BASE);
- uart_init();
- console_init();
-
- // Halt if there was a built in self test failure
- report_bist_failure(bist);
-
-// print_pci_devices();
-
- // If this is a warm boot, some initialization can be skipped
-
- if (!bios_reset_detected())
- {
- enable_smbus();
-// dump_spd_registers(&memctrl[0]);
-// dump_smbus_registers();
-
-// memreset_setup(); No-op for this chipset
- sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl);
- }
-
- // NOTE: ROMCC dies with an internal compiler error
- // if the following line is removed.
- print_debug("SDRAM is up.\r\n");
-}
+#define ASSEMBLY 1
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+#include "southbridge/intel/i82801ca/i82801ca_early_smbus.c"
+#include "northbridge/intel/e7501/raminit.h"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/intel/e7501/debug.c"
+#include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
+
+#define SUPERIO_PORT 0x2e
+#define SERIAL_DEV PNP_DEV(SUPERIO_PORT, LPC47B272_SP1)
+
+static void hard_reset(void)
+{
+ outb(0x0e, 0x0cf9);
+}
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+ /* nothing to do */
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/intel/e7501/raminit.c"
+#include "northbridge/intel/e7501/reset_test.c"
+#include "sdram/generic_sdram.c"
+
+
+// This function MUST appear last (ROMCC limitation)
+static void main(unsigned long bist)
+{
+ static const struct mem_controller memctrl[] = {
+ {
+ .d0 = PCI_DEV(0, 0, 0),
+ .d0f1 = PCI_DEV(0, 0, 1),
+ .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },
+ .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },
+ },
+ };
+
+ if (bist == 0)
+ {
+ // Skip this if there was a built in self test failure
+
+ early_mtrr_init();
+ enable_lapic();
+ }
+
+ // Get the serial port running and print a welcome banner
+
+ lpc47b272_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ uart_init();
+ console_init();
+
+ // Halt if there was a built in self test failure
+ report_bist_failure(bist);
+
+// print_pci_devices();
+
+ // If this is a warm boot, some initialization can be skipped
+
+ if (!bios_reset_detected())
+ {
+ enable_smbus();
+// dump_spd_registers(&memctrl[0]);
+// dump_smbus_registers();
+
+// memreset_setup(); No-op for this chipset
+ sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl);
+ }
+
+ // NOTE: ROMCC dies with an internal compiler error
+ // if the following line is removed.
+ print_debug("SDRAM is up.\r\n");
+}
diff --git a/src/mainboard/intel/xe7501devkit/bus.h b/src/mainboard/intel/xe7501devkit/bus.h
index 0a99bb2808..84661ddb36 100644
--- a/src/mainboard/intel/xe7501devkit/bus.h
+++ b/src/mainboard/intel/xe7501devkit/bus.h
@@ -1,17 +1,17 @@
-#ifndef XE7501DEVKIT_BUS_H_INCLUDED
-#define XE7501DEVKIT_BUS_H_INCLUDED
-
-// These were determined by seeing how LinuxBIOS enumerates the various
-// PCI (and PCI-like) buses on the board.
-
-#define PCI_BUS_CHIPSET 0
-#define PCI_BUS_E7501_HI_B 1 // P64H2#2
-#define PCI_BUS_P64H2_2_B 2 // P64H2#2 bus B
-#define PCI_BUS_P64H2_2_A 3 // P64H2#2 bus A
-#define PCI_BUS_E7501_HI_D 4 // P64H2#1
-#define PCI_BUS_P64H2_1_B 5 // P64H2#1 bus B
-#define PCI_BUS_P64H2_1_A 6 // P64H2#1 bus A
-#define PCI_BUS_ICH3 7 // ICH3-S
-#define SUPERIO_BUS 8 // (arbitrary but unique bus #)
-
-#endif // XE7501DEVKIT_BUS_H_INCLUDED
+#ifndef XE7501DEVKIT_BUS_H_INCLUDED
+#define XE7501DEVKIT_BUS_H_INCLUDED
+
+// These were determined by seeing how LinuxBIOS enumerates the various
+// PCI (and PCI-like) buses on the board.
+
+#define PCI_BUS_CHIPSET 0
+#define PCI_BUS_E7501_HI_B 1 // P64H2#2
+#define PCI_BUS_P64H2_2_B 2 // P64H2#2 bus B
+#define PCI_BUS_P64H2_2_A 3 // P64H2#2 bus A
+#define PCI_BUS_E7501_HI_D 4 // P64H2#1
+#define PCI_BUS_P64H2_1_B 5 // P64H2#1 bus B
+#define PCI_BUS_P64H2_1_A 6 // P64H2#1 bus A
+#define PCI_BUS_ICH3 7 // ICH3-S
+#define SUPERIO_BUS 8 // (arbitrary but unique bus #)
+
+#endif // XE7501DEVKIT_BUS_H_INCLUDED
diff --git a/src/mainboard/intel/xe7501devkit/chip.h b/src/mainboard/intel/xe7501devkit/chip.h
index b0885c1a54..12a9127ff2 100644
--- a/src/mainboard/intel/xe7501devkit/chip.h
+++ b/src/mainboard/intel/xe7501devkit/chip.h
@@ -1,6 +1,6 @@
-extern unsigned char _vgarom_start[];
-
-extern struct chip_operations mainboard_intel_xe7501devkit_ops;
-
-struct mainboard_intel_xe7501devkit_config {
-};
+extern unsigned char _vgarom_start[];
+
+extern struct chip_operations mainboard_intel_xe7501devkit_ops;
+
+struct mainboard_intel_xe7501devkit_config {
+};
diff --git a/src/mainboard/intel/xe7501devkit/cmos.layout b/src/mainboard/intel/xe7501devkit/cmos.layout
index 1aa038d34d..57139c1cd5 100644
--- a/src/mainboard/intel/xe7501devkit/cmos.layout
+++ b/src/mainboard/intel/xe7501devkit/cmos.layout
@@ -7,8 +7,8 @@ entries
0 512 r 0 reserved_memory1 # We know nothing about the factory BIOS
512 512 r 0 reserved_memory2 # More factory BIOS
-# Work in progress.
-# This is where we would put the LB RTC_BOOT_BYTE options once the code
+# Work in progress.
+# This is where we would put the LB RTC_BOOT_BYTE options once the code
# supports finding them there.
#1024 1 e 4 boot_option
#1025 1 e 4 last_boot
diff --git a/src/mainboard/intel/xe7501devkit/failover.c b/src/mainboard/intel/xe7501devkit/failover.c
index 68a1fec4eb..5ec12d67cd 100644
--- a/src/mainboard/intel/xe7501devkit/failover.c
+++ b/src/mainboard/intel/xe7501devkit/failover.c
@@ -1,47 +1,47 @@
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/intel/i82801ca/cmos_failover.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/intel/e7501/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
- /* Is this a deliberate reset by the bios */
- if (bios_reset_detected() && last_boot_normal()) {
- goto normal_image;
- }
- /* This is the primary cpu how should I boot? */
- else {
-
- check_cmos_failed();
-
- if (do_normal_boot()) {
- goto normal_image;
- }
- else {
- goto fallback_image;
- }
- }
- normal_image:
- asm volatile ("jmp __normal_image"
- : /* outputs */
- : "a" (bist) /* inputs */
- : /* clobbers */
- );
-#if 0
- cpu_reset:
- asm volatile ("jmp __cpu_reset"
- : /* outputs */
- : "a"(bist) /* inputs */
- : /* clobbers */
- );
-#endif
- fallback_image:
- return bist;
-}
+#define ASSEMBLY 1
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "pc80/mc146818rtc_early.c"
+#include "southbridge/intel/i82801ca/cmos_failover.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/intel/e7501/reset_test.c"
+
+static unsigned long main(unsigned long bist)
+{
+ /* Is this a deliberate reset by the bios */
+ if (bios_reset_detected() && last_boot_normal()) {
+ goto normal_image;
+ }
+ /* This is the primary cpu how should I boot? */
+ else {
+
+ check_cmos_failed();
+
+ if (do_normal_boot()) {
+ goto normal_image;
+ }
+ else {
+ goto fallback_image;
+ }
+ }
+ normal_image:
+ asm volatile ("jmp __normal_image"
+ : /* outputs */
+ : "a" (bist) /* inputs */
+ : /* clobbers */
+ );
+#if 0
+ cpu_reset:
+ asm volatile ("jmp __cpu_reset"
+ : /* outputs */
+ : "a"(bist) /* inputs */
+ : /* clobbers */
+ );
+#endif
+ fallback_image:
+ return bist;
+}
diff --git a/src/mainboard/intel/xe7501devkit/ioapic.h b/src/mainboard/intel/xe7501devkit/ioapic.h
index 6db3d949f6..642c04519f 100644
--- a/src/mainboard/intel/xe7501devkit/ioapic.h
+++ b/src/mainboard/intel/xe7501devkit/ioapic.h
@@ -1,11 +1,11 @@
-// IOAPIC addresses determined by LinuxBIOS enumeration.
-// Someday add functions to get APIC IDs and versions from the chips themselves.
-
-#define IOAPIC_ICH3 2
-#define IOAPIC_P64H2_2_BUS_B 3 // IOAPIC 3 at 01:1c.0 MBAR = fe300000 DataAddr = fe300010
-#define IOAPIC_P64H2_2_BUS_A 4 // IOAPIC 4 at 01:1e.0 MBAR = fe301000 DataAddr = fe301010
-#define IOAPIC_P64H2_1_BUS_B 5 // IOAPIC 5 at 04:1c.0 MBAR = fe500000 DataAddr = fe500010
-#define IOAPIC_P64H2_1_BUS_A 8 // IOAPIC 8 at 04:1e.0 MBAR = fe501000 DataAddr = fe501010
-
-#define P64H2_IOAPIC_VERSION 0x20
-#define INTEL_IOAPIC_NUM_INTERRUPTS 24 // Both ICH-3 and P64-H2
+// IOAPIC addresses determined by LinuxBIOS enumeration.
+// Someday add functions to get APIC IDs and versions from the chips themselves.
+
+#define IOAPIC_ICH3 2
+#define IOAPIC_P64H2_2_BUS_B 3 // IOAPIC 3 at 01:1c.0 MBAR = fe300000 DataAddr = fe300010
+#define IOAPIC_P64H2_2_BUS_A 4 // IOAPIC 4 at 01:1e.0 MBAR = fe301000 DataAddr = fe301010
+#define IOAPIC_P64H2_1_BUS_B 5 // IOAPIC 5 at 04:1c.0 MBAR = fe500000 DataAddr = fe500010
+#define IOAPIC_P64H2_1_BUS_A 8 // IOAPIC 8 at 04:1e.0 MBAR = fe501000 DataAddr = fe501010
+
+#define P64H2_IOAPIC_VERSION 0x20
+#define INTEL_IOAPIC_NUM_INTERRUPTS 24 // Both ICH-3 and P64-H2
diff --git a/src/mainboard/intel/xe7501devkit/irq_tables.c b/src/mainboard/intel/xe7501devkit/irq_tables.c
index c30bf2daf2..0134f3be6d 100644
--- a/src/mainboard/intel/xe7501devkit/irq_tables.c
+++ b/src/mainboard/intel/xe7501devkit/irq_tables.c
@@ -1,74 +1,74 @@
-/* Run checkpir to verify any changes to this table...
- Documentation at : http://www.microsoft.com/whdc/archive/pciirq.mspx
-*/
-
-#include <arch/pirq_routing.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include "bus.h"
-
-#define UNUSED_INTERRUPT {0, 0}
-#define PIRQ_A 0x60
-#define PIRQ_B 0x61
-#define PIRQ_C 0x62
-#define PIRQ_D 0x63
-#define PIRQ_E 0x68
-#define PIRQ_F 0x69
-#define PIRQ_G 0x6A
-#define PIRQ_H 0x6B
-
-const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE,
- PIRQ_VERSION,
- 32 + 12*sizeof(struct irq_info), // Size of this struct in bytes
- 0, // PCI bus number on which the interrupt router resides
- PCI_DEVFN(31, 0), // PCI device/function number of the interrupt router
- 0, // PCI-exclusive IRQ bitmap
- PCI_VENDOR_ID_INTEL, // Vendor ID of compatible PCI interrupt router
- PCI_DEVICE_ID_INTEL_82801CA_LPC, // Device ID of compatible PCI interrupt router
- 0, // Additional miniport information
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, // Reserved, must be zero
- 0xB1, // Checksum of the entire structure (causes 8-bit sum == 0)
- {
- // NOTE: For 82801, a nonzero link value is a pointer to a PIRQ[n]_ROUT register in PCI configuration space
- // This was determined from linux-2.6.11/arch/i386/pci/irq.c
- // bitmap of 0xdcf8 == routable to IRQ3-IRQ7, IRQ10-IRQ12, or IRQ14-IRQ15
- // ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13
- // Not sure why IRQ9 isn't routable (inherited from Tyan S2735)
-
- // INTA# INTB# INTC# INTD#
- // bus, device # {link , bitmap}, {link , bitmap}, {link , bitmap}, {link , bitmap}, slot, rfu
-
- {PCI_BUS_CHIPSET, PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // IDE / SMBus
- {PCI_BUS_CHIPSET, PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, UNUSED_INTERRUPT}, 0, 0}, // USB 1.1
-
- // P64H2#2 Bus A
- {PCI_BUS_P64H2_2_A, PCI_DEVFN(1, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // SCSI
- // NOTE: Hotplug disabled on this bus
-
- // P64H2#2 Bus B
- {PCI_BUS_P64H2_2_B, PCI_DEVFN(1, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 23, 0}, // Slot 2A (J23)
- {PCI_BUS_P64H2_2_B, PCI_DEVFN(2, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 24, 0}, // Slot 2B (J24)
- {PCI_BUS_P64H2_2_B, PCI_DEVFN(3, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 25, 0}, // Slot 2C (J25)
- {PCI_BUS_P64H2_2_B, PCI_DEVFN(4, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 12, 0}, // Slot 2D (J12)
- // NOTE: Hotplug disabled on this bus
-
- // P64H2#1 Bus A
- {PCI_BUS_P64H2_1_A, PCI_DEVFN(1, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}}, 20, 0}, // Slot 1A (J20)
- // NOTE: Hotplug disabled on this bus
-
- // P64H2#1 Bus B
- {PCI_BUS_P64H2_1_B, PCI_DEVFN(1, 0), {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // GB Ethernet
- {PCI_BUS_P64H2_1_B, PCI_DEVFN(2, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}}, 21, 0}, // Slot 1B (J21)
- // NOTE: Hotplug disabled on this bus
-
- // ICH-3 PCI bus
- {PCI_BUS_ICH3, PCI_DEVFN(0, 0), {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // Video
- {PCI_BUS_ICH3, PCI_DEVFN(2, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 11, 0}, // Debug slot (J11)
- }
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr);
-}
+/* Run checkpir to verify any changes to this table...
+ Documentation at : http://www.microsoft.com/whdc/archive/pciirq.mspx
+*/
+
+#include <arch/pirq_routing.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include "bus.h"
+
+#define UNUSED_INTERRUPT {0, 0}
+#define PIRQ_A 0x60
+#define PIRQ_B 0x61
+#define PIRQ_C 0x62
+#define PIRQ_D 0x63
+#define PIRQ_E 0x68
+#define PIRQ_F 0x69
+#define PIRQ_G 0x6A
+#define PIRQ_H 0x6B
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE,
+ PIRQ_VERSION,
+ 32 + 12*sizeof(struct irq_info), // Size of this struct in bytes
+ 0, // PCI bus number on which the interrupt router resides
+ PCI_DEVFN(31, 0), // PCI device/function number of the interrupt router
+ 0, // PCI-exclusive IRQ bitmap
+ PCI_VENDOR_ID_INTEL, // Vendor ID of compatible PCI interrupt router
+ PCI_DEVICE_ID_INTEL_82801CA_LPC, // Device ID of compatible PCI interrupt router
+ 0, // Additional miniport information
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, // Reserved, must be zero
+ 0xB1, // Checksum of the entire structure (causes 8-bit sum == 0)
+ {
+ // NOTE: For 82801, a nonzero link value is a pointer to a PIRQ[n]_ROUT register in PCI configuration space
+ // This was determined from linux-2.6.11/arch/i386/pci/irq.c
+ // bitmap of 0xdcf8 == routable to IRQ3-IRQ7, IRQ10-IRQ12, or IRQ14-IRQ15
+ // ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13
+ // Not sure why IRQ9 isn't routable (inherited from Tyan S2735)
+
+ // INTA# INTB# INTC# INTD#
+ // bus, device # {link , bitmap}, {link , bitmap}, {link , bitmap}, {link , bitmap}, slot, rfu
+
+ {PCI_BUS_CHIPSET, PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // IDE / SMBus
+ {PCI_BUS_CHIPSET, PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, UNUSED_INTERRUPT}, 0, 0}, // USB 1.1
+
+ // P64H2#2 Bus A
+ {PCI_BUS_P64H2_2_A, PCI_DEVFN(1, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // SCSI
+ // NOTE: Hotplug disabled on this bus
+
+ // P64H2#2 Bus B
+ {PCI_BUS_P64H2_2_B, PCI_DEVFN(1, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 23, 0}, // Slot 2A (J23)
+ {PCI_BUS_P64H2_2_B, PCI_DEVFN(2, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 24, 0}, // Slot 2B (J24)
+ {PCI_BUS_P64H2_2_B, PCI_DEVFN(3, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 25, 0}, // Slot 2C (J25)
+ {PCI_BUS_P64H2_2_B, PCI_DEVFN(4, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 12, 0}, // Slot 2D (J12)
+ // NOTE: Hotplug disabled on this bus
+
+ // P64H2#1 Bus A
+ {PCI_BUS_P64H2_1_A, PCI_DEVFN(1, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}}, 20, 0}, // Slot 1A (J20)
+ // NOTE: Hotplug disabled on this bus
+
+ // P64H2#1 Bus B
+ {PCI_BUS_P64H2_1_B, PCI_DEVFN(1, 0), {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // GB Ethernet
+ {PCI_BUS_P64H2_1_B, PCI_DEVFN(2, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}}, 21, 0}, // Slot 1B (J21)
+ // NOTE: Hotplug disabled on this bus
+
+ // ICH-3 PCI bus
+ {PCI_BUS_ICH3, PCI_DEVFN(0, 0), {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // Video
+ {PCI_BUS_ICH3, PCI_DEVFN(2, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 11, 0}, // Debug slot (J11)
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr);
+}
diff --git a/src/mainboard/intel/xe7501devkit/mainboard.c b/src/mainboard/intel/xe7501devkit/mainboard.c
index 38639b9d39..158b0183e2 100644
--- a/src/mainboard/intel/xe7501devkit/mainboard.c
+++ b/src/mainboard/intel/xe7501devkit/mainboard.c
@@ -1,12 +1,12 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "chip.h"
-
-#if CONFIG_CHIP_NAME == 1
-struct chip_operations mainboard_intel_xe7501devkit_ops = {
- CHIP_NAME("Intel Xeon E7501 DevKit mainboard")
-};
-#endif
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "chip.h"
+
+#if CONFIG_CHIP_NAME == 1
+struct chip_operations mainboard_intel_xe7501devkit_ops = {
+ CHIP_NAME("Intel Xeon E7501 DevKit mainboard")
+};
+#endif
diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c
index 7dae29c450..0da0676d35 100644
--- a/src/mainboard/intel/xe7501devkit/mptable.c
+++ b/src/mainboard/intel/xe7501devkit/mptable.c
@@ -1,180 +1,180 @@
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <assert.h>
-#include "bus.h"
-#include "ioapic.h"
-
-// Generate MP-table IRQ numbers for PCI devices.
-#define INT_A 0
-#define INT_B 1
-#define INT_C 2
-#define INT_D 3
-#define PCI_IRQ(dev, intLine) (((dev)<<2) | intLine)
-
-
-void xe7501devkit_register_buses(struct mp_config_table *mc)
-{
- // Bus ID, Bus Type
- smp_write_bus(mc, PCI_BUS_CHIPSET, BUSTYPE_PCI);
- smp_write_bus(mc, PCI_BUS_E7501_HI_B, BUSTYPE_PCI);
- smp_write_bus(mc, PCI_BUS_P64H2_2_B, BUSTYPE_PCI);
- smp_write_bus(mc, PCI_BUS_P64H2_2_A, BUSTYPE_PCI);
- smp_write_bus(mc, PCI_BUS_E7501_HI_D, BUSTYPE_PCI);
- smp_write_bus(mc, PCI_BUS_P64H2_1_B, BUSTYPE_PCI);
- smp_write_bus(mc, PCI_BUS_P64H2_1_A, BUSTYPE_PCI);
- smp_write_bus(mc, PCI_BUS_ICH3, BUSTYPE_PCI);
- smp_write_bus(mc, SUPERIO_BUS, BUSTYPE_ISA);
-}
-
-void xe7501devkit_register_ioapics(struct mp_config_table *mc)
-{
- device_t dev;
- struct resource *res;
-
- // TODO: Gack. This is REALLY ugly.
-
- // Southbridge IOAPIC
- smp_write_ioapic(mc, IOAPIC_ICH3, 0x20, 0xfec00000); // APIC ID, Version, Address
-
- // P64H2#2 Bus A IOAPIC
- dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
- if (!dev)
- BUG(); // Config.lb error?
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- smp_write_ioapic(mc, IOAPIC_P64H2_2_BUS_A, P64H2_IOAPIC_VERSION, res->base);
-
- // P64H2#2 Bus B IOAPIC
- dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
- if (!dev)
- BUG(); // Config.lb error?
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- smp_write_ioapic(mc, IOAPIC_P64H2_2_BUS_B, P64H2_IOAPIC_VERSION, res->base);
-
-
- // P64H2#1 Bus A IOAPIC
- dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));
- if (!dev)
- BUG(); // Config.lb error?
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_A, P64H2_IOAPIC_VERSION, res->base);
-
- // P64H2#1 Bus B IOAPIC
- dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));
- if (!dev)
- BUG(); // Config.lb error?
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_B, P64H2_IOAPIC_VERSION, res->base);
-}
-
-void xe7501devkit_register_interrupts(struct mp_config_table *mc)
-{
- // Chipset PCI bus
- // Type Trigger | Polarity Bus ID IRQ APIC ID PIN#
- smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, PCI_BUS_CHIPSET, 0, MP_APIC_ALL, 0);
- smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, PCI_BUS_CHIPSET, 0, MP_APIC_ALL, 1);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_A), IOAPIC_ICH3, 16); // USB 1.1 Controller #1
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(31, INT_B), IOAPIC_ICH3, 17); // SMBus
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_C), IOAPIC_ICH3, 18); // USB 1.1 Controller #3
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(31, INT_C), IOAPIC_ICH3, 18); // IDE
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_D), IOAPIC_ICH3, 19); // USB 1.1 Controller #2
-
- // P64H2#2 Bus B
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_A), IOAPIC_P64H2_2_BUS_B, 0); // Slot 2A (J23)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_B), IOAPIC_P64H2_2_BUS_B, 1); // Slot 2A (J23)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_C), IOAPIC_P64H2_2_BUS_B, 2); // Slot 2A (J23)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_D), IOAPIC_P64H2_2_BUS_B, 3); // Slot 2A (J23)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_A), IOAPIC_P64H2_2_BUS_B, 4); // Slot 2B (J24)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_B), IOAPIC_P64H2_2_BUS_B, 5); // Slot 2B (J24)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_C), IOAPIC_P64H2_2_BUS_B, 6); // Slot 2B (J24)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_D), IOAPIC_P64H2_2_BUS_B, 7); // Slot 2B (J24)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_A), IOAPIC_P64H2_2_BUS_B, 8); // Slot 2C (J25)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_B), IOAPIC_P64H2_2_BUS_B, 9); // Slot 2C (J25)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_C), IOAPIC_P64H2_2_BUS_B, 10); // Slot 2C (J25)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_D), IOAPIC_P64H2_2_BUS_B, 11); // Slot 2C (J25)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_A), IOAPIC_P64H2_2_BUS_B, 12); // Slot 2D (J12)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_B), IOAPIC_P64H2_2_BUS_B, 13); // Slot 2D (J12)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_C), IOAPIC_P64H2_2_BUS_B, 14); // Slot 2D (J12)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_D), IOAPIC_P64H2_2_BUS_B, 15); // Slot 2D (J12)
-
- // P64H2#2 Bus A
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_A, PCI_IRQ(1, INT_A), IOAPIC_P64H2_2_BUS_A, 0); // SCSI
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_A, PCI_IRQ(1, INT_B), IOAPIC_P64H2_2_BUS_A, 1); // SCSI
-
- // P64H2#1 Bus B
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(1, INT_A), IOAPIC_P64H2_1_BUS_B, 0); // GB Ethernet
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_A), IOAPIC_P64H2_1_BUS_B, 4); // Slot 1B (J21)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_B), IOAPIC_P64H2_1_BUS_B, 5); // Slot 1B (J21)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_C), IOAPIC_P64H2_1_BUS_B, 6); // Slot 1B (J21)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_D), IOAPIC_P64H2_1_BUS_B, 7); // Slot 1B (J21)
-
- // P64H2#1 Bus A
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_A), IOAPIC_P64H2_1_BUS_A, 0); // Slot 1A (J20)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_B), IOAPIC_P64H2_1_BUS_A, 1); // Slot 1A (J20)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_C), IOAPIC_P64H2_1_BUS_A, 2); // Slot 1A (J20)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_D), IOAPIC_P64H2_1_BUS_A, 3); // Slot 1A (J20)
-
- // ICH-3
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(0, INT_A), IOAPIC_ICH3, 16); // Video
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_A), IOAPIC_ICH3, 18); // Debug slot (J11)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_B), IOAPIC_ICH3, 19); // Debug slot (J11)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_C), IOAPIC_ICH3, 16); // Debug slot (J11)
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_D), IOAPIC_ICH3, 17); // Debug slot (J11)
-
- // TODO: Not sure how to handle BT_INTR# signals from the P64H2s. Do we even need to, in APIC mode?
-
- // Super I/O (ISA interrupts)
- smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 0, IOAPIC_ICH3, 0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 1, IOAPIC_ICH3, 1);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 0, IOAPIC_ICH3, 2);
-
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 3, IOAPIC_ICH3, 3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 4, IOAPIC_ICH3, 4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 6, IOAPIC_ICH3, 6);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 8, IOAPIC_ICH3, 8);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 9, IOAPIC_ICH3, 9);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 12, IOAPIC_ICH3, 12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 13, IOAPIC_ICH3, 13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 14, IOAPIC_ICH3, 14);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 15, IOAPIC_ICH3, 15);
-}
-
-void* smp_write_config_table(void* v)
-{
- static const char sig[4] = MPC_SIGNATURE;
- static const char oem[8] = "INTEL ";
- static const char productid[12] = "XE7501DEVKIT";
- struct mp_config_table *mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
- memset(mc, 0, sizeof(*mc));
-
- memcpy(mc->mpc_signature, sig, sizeof(sig));
- memcpy(mc->mpc_oem, oem, sizeof(oem));
- memcpy(mc->mpc_productid, productid, sizeof(productid));
-
- mc->mpc_length = sizeof(*mc); // initially just the header
- mc->mpc_spec = 0x04; // Multiprocessing Spec V1.4
- mc->mpc_lapic = LAPIC_ADDR;
-
- smp_write_processors(mc);
-
- xe7501devkit_register_buses(mc);
- xe7501devkit_register_ioapics(mc);
- xe7501devkit_register_interrupts(mc);
-
- /* Compute the checksums */
- mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
- mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
- printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
-
- return smp_next_mpe_entry(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr);
- return (unsigned long)smp_write_config_table(v);
-}
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <assert.h>
+#include "bus.h"
+#include "ioapic.h"
+
+// Generate MP-table IRQ numbers for PCI devices.
+#define INT_A 0
+#define INT_B 1
+#define INT_C 2
+#define INT_D 3
+#define PCI_IRQ(dev, intLine) (((dev)<<2) | intLine)
+
+
+void xe7501devkit_register_buses(struct mp_config_table *mc)
+{
+ // Bus ID, Bus Type
+ smp_write_bus(mc, PCI_BUS_CHIPSET, BUSTYPE_PCI);
+ smp_write_bus(mc, PCI_BUS_E7501_HI_B, BUSTYPE_PCI);
+ smp_write_bus(mc, PCI_BUS_P64H2_2_B, BUSTYPE_PCI);
+ smp_write_bus(mc, PCI_BUS_P64H2_2_A, BUSTYPE_PCI);
+ smp_write_bus(mc, PCI_BUS_E7501_HI_D, BUSTYPE_PCI);
+ smp_write_bus(mc, PCI_BUS_P64H2_1_B, BUSTYPE_PCI);
+ smp_write_bus(mc, PCI_BUS_P64H2_1_A, BUSTYPE_PCI);
+ smp_write_bus(mc, PCI_BUS_ICH3, BUSTYPE_PCI);
+ smp_write_bus(mc, SUPERIO_BUS, BUSTYPE_ISA);
+}
+
+void xe7501devkit_register_ioapics(struct mp_config_table *mc)
+{
+ device_t dev;
+ struct resource *res;
+
+ // TODO: Gack. This is REALLY ugly.
+
+ // Southbridge IOAPIC
+ smp_write_ioapic(mc, IOAPIC_ICH3, 0x20, 0xfec00000); // APIC ID, Version, Address
+
+ // P64H2#2 Bus A IOAPIC
+ dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
+ if (!dev)
+ BUG(); // Config.lb error?
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ smp_write_ioapic(mc, IOAPIC_P64H2_2_BUS_A, P64H2_IOAPIC_VERSION, res->base);
+
+ // P64H2#2 Bus B IOAPIC
+ dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
+ if (!dev)
+ BUG(); // Config.lb error?
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ smp_write_ioapic(mc, IOAPIC_P64H2_2_BUS_B, P64H2_IOAPIC_VERSION, res->base);
+
+
+ // P64H2#1 Bus A IOAPIC
+ dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));
+ if (!dev)
+ BUG(); // Config.lb error?
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_A, P64H2_IOAPIC_VERSION, res->base);
+
+ // P64H2#1 Bus B IOAPIC
+ dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));
+ if (!dev)
+ BUG(); // Config.lb error?
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_B, P64H2_IOAPIC_VERSION, res->base);
+}
+
+void xe7501devkit_register_interrupts(struct mp_config_table *mc)
+{
+ // Chipset PCI bus
+ // Type Trigger | Polarity Bus ID IRQ APIC ID PIN#
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, PCI_BUS_CHIPSET, 0, MP_APIC_ALL, 0);
+ smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, PCI_BUS_CHIPSET, 0, MP_APIC_ALL, 1);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_A), IOAPIC_ICH3, 16); // USB 1.1 Controller #1
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(31, INT_B), IOAPIC_ICH3, 17); // SMBus
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_C), IOAPIC_ICH3, 18); // USB 1.1 Controller #3
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(31, INT_C), IOAPIC_ICH3, 18); // IDE
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_D), IOAPIC_ICH3, 19); // USB 1.1 Controller #2
+
+ // P64H2#2 Bus B
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_A), IOAPIC_P64H2_2_BUS_B, 0); // Slot 2A (J23)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_B), IOAPIC_P64H2_2_BUS_B, 1); // Slot 2A (J23)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_C), IOAPIC_P64H2_2_BUS_B, 2); // Slot 2A (J23)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_D), IOAPIC_P64H2_2_BUS_B, 3); // Slot 2A (J23)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_A), IOAPIC_P64H2_2_BUS_B, 4); // Slot 2B (J24)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_B), IOAPIC_P64H2_2_BUS_B, 5); // Slot 2B (J24)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_C), IOAPIC_P64H2_2_BUS_B, 6); // Slot 2B (J24)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_D), IOAPIC_P64H2_2_BUS_B, 7); // Slot 2B (J24)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_A), IOAPIC_P64H2_2_BUS_B, 8); // Slot 2C (J25)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_B), IOAPIC_P64H2_2_BUS_B, 9); // Slot 2C (J25)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_C), IOAPIC_P64H2_2_BUS_B, 10); // Slot 2C (J25)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_D), IOAPIC_P64H2_2_BUS_B, 11); // Slot 2C (J25)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_A), IOAPIC_P64H2_2_BUS_B, 12); // Slot 2D (J12)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_B), IOAPIC_P64H2_2_BUS_B, 13); // Slot 2D (J12)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_C), IOAPIC_P64H2_2_BUS_B, 14); // Slot 2D (J12)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_D), IOAPIC_P64H2_2_BUS_B, 15); // Slot 2D (J12)
+
+ // P64H2#2 Bus A
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_A, PCI_IRQ(1, INT_A), IOAPIC_P64H2_2_BUS_A, 0); // SCSI
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_A, PCI_IRQ(1, INT_B), IOAPIC_P64H2_2_BUS_A, 1); // SCSI
+
+ // P64H2#1 Bus B
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(1, INT_A), IOAPIC_P64H2_1_BUS_B, 0); // GB Ethernet
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_A), IOAPIC_P64H2_1_BUS_B, 4); // Slot 1B (J21)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_B), IOAPIC_P64H2_1_BUS_B, 5); // Slot 1B (J21)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_C), IOAPIC_P64H2_1_BUS_B, 6); // Slot 1B (J21)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_D), IOAPIC_P64H2_1_BUS_B, 7); // Slot 1B (J21)
+
+ // P64H2#1 Bus A
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_A), IOAPIC_P64H2_1_BUS_A, 0); // Slot 1A (J20)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_B), IOAPIC_P64H2_1_BUS_A, 1); // Slot 1A (J20)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_C), IOAPIC_P64H2_1_BUS_A, 2); // Slot 1A (J20)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_D), IOAPIC_P64H2_1_BUS_A, 3); // Slot 1A (J20)
+
+ // ICH-3
+
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(0, INT_A), IOAPIC_ICH3, 16); // Video
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_A), IOAPIC_ICH3, 18); // Debug slot (J11)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_B), IOAPIC_ICH3, 19); // Debug slot (J11)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_C), IOAPIC_ICH3, 16); // Debug slot (J11)
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_D), IOAPIC_ICH3, 17); // Debug slot (J11)
+
+ // TODO: Not sure how to handle BT_INTR# signals from the P64H2s. Do we even need to, in APIC mode?
+
+ // Super I/O (ISA interrupts)
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 0, IOAPIC_ICH3, 0);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 1, IOAPIC_ICH3, 1);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 0, IOAPIC_ICH3, 2);
+
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 3, IOAPIC_ICH3, 3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 4, IOAPIC_ICH3, 4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 6, IOAPIC_ICH3, 6);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 8, IOAPIC_ICH3, 8);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 9, IOAPIC_ICH3, 9);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 12, IOAPIC_ICH3, 12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 13, IOAPIC_ICH3, 13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 14, IOAPIC_ICH3, 14);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 15, IOAPIC_ICH3, 15);
+}
+
+void* smp_write_config_table(void* v)
+{
+ static const char sig[4] = MPC_SIGNATURE;
+ static const char oem[8] = "INTEL ";
+ static const char productid[12] = "XE7501DEVKIT";
+ struct mp_config_table *mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+ memset(mc, 0, sizeof(*mc));
+
+ memcpy(mc->mpc_signature, sig, sizeof(sig));
+ memcpy(mc->mpc_oem, oem, sizeof(oem));
+ memcpy(mc->mpc_productid, productid, sizeof(productid));
+
+ mc->mpc_length = sizeof(*mc); // initially just the header
+ mc->mpc_spec = 0x04; // Multiprocessing Spec V1.4
+ mc->mpc_lapic = LAPIC_ADDR;
+
+ smp_write_processors(mc);
+
+ xe7501devkit_register_buses(mc);
+ xe7501devkit_register_ioapics(mc);
+ xe7501devkit_register_interrupts(mc);
+
+ /* Compute the checksums */
+ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+ mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+ printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));
+
+ return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr);
+ return (unsigned long)smp_write_config_table(v);
+}